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500054d november 2002 m28975 zipwireplus ? g.shdsl transceiver with embedded microprocessor data sheet
ii mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d ordering information marketing name description package ambient temperature range m28945-33 dsp/framer 176-pin lqfp 48-pin etqfp ?40 c to +85 c m28945-13 dsp/framer 13 13 mm fpbga 48-pin etqfp ?40 c to +85 c M28927-29 afe/line driver 6 x 6 mm 48-pin etqfp ?40 c to +85 c revision history revision level date description a advance june 2000 initial release. b advance august 2000 added copyright information to footer on front page. no technical information was changed. c advance january 2001 updated pin-out and description major overhaul to reflect m28975 functionality d advance january 2001 added marketing number to front page. no technical information was changed. a preliminary may 2001 new document number 500054a. formerly known as 101083d. b preliminary october 2001 new document number 500054b. document 500054b was separated into two documents. this document contains the hardware information. see m28975 zipwireplus g.shdsl transceiver with embedded micropro cessor programmer reference manual for the software information. deleted lga package information. c preliminary november 2002 removed erroneous operation modes. d preliminary november 2002 corrected figures and tables. ? 2002 , mindspeed technologies?, a conexant business a ll rights reserved. information in this document is provi ded in connection with mindspeed technologies (?minds peed?) products. these materials are provided by mindspeed as a service to its customers and may be used for in formational purposes only. mi ndspeed assumes no responsibility fo r errors or omissions in these materials. mindspeed may make changes to specificati ons and product descriptions at any time, without notice . mindspeed makes no commitment to update the information and shall have no re sponsibility whatsoever for conflicts or incompatibilities ar ising from future changes to its specific ations and product descriptions. no license, express or implied, by est oppel or otherwise, to any intellectual proper ty rights is granted by this document. exce pt as provided in mindspeed?s terms and conditions of sale for such products, mindspeed assumes no liability whatsoever. these materials are provided ?as is? without warranty of any kind, either express or implied, relating to sale and/or use of mindspeed products including li ability or warranties relating to fitness for a particular purpose, consequential or incidental dama ges, merchantability, or infringement of any patent, copyright or other intellectual property right. mindspeed further does not warrant the accuracy or completeness of the information, text, graphics or other items contained within these materials. mindspeed shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesaving or life sustaini ng applications. mindspeed customers using o r selling mindspeed products for use in such applicat ions do so at their own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale. the following are trademarks of conexant systems, inc.: mindspeed technologies?, the mindspeed? l ogo, and ?build it first??. pr oduct names or services listed in this public ation are for identification purposes only, and may be trademarks of third parties. thir d-party brands and names are the property of their respective owners. for additional disclaimer informati on, please consult minds peed technologies legal in formation posted at www.minds peed.com which is incorporated by reference.
500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential iii m28975 zipwireplus ? g.shdsl transceiver with embedded microprocessor multimode operation: g.shdsl+, hdsl2, sdsl, and hdsl the zipwireplus multimode dsl solution goes beyond simple compliance to the itu-t g.shdsl standard by supporting the optional enhanced performance asymmetr ical psd (epap) mode of operation. in addition, it is comp liant with the ansi hdsl2 standard (ansi t1.418) and provides interoperability with mindspeed?s market-leading zipwire transceivers through operation in 2b1q multirate mode. the 2b1q mode includes support of autobaud for sdsl interoperability, rate optimiz ation and fast connect times, as well as standards-based hdsl operation. the zipwireplus also supports mindspeed?s own proprieta ry modes, like 32-pam, 64 kbps and 4.6 mbps operation, which provide enhanced spectral compatibility, extended subscri ber line reach, and high-speed operation. all modes are supported by a single hardware circuit (i.e., one transformer, crystal, and hybrid ) and can be configured in real time via software control. functional block diagram preliminary information this document contains info rmation on a new product. the parametric information, although not fully characterized, is the result of testing initial devices. distinguishing features ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
iv mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d embedded microprocessor the zipwireplus chip set includes an embedded microprocessor and a full suite of software that facilitate speedy and simplified development of systems compliant with all applicable itu, ansi, and etsi standards. the embedded microprocessor and software handle the eoc processing and many other functions often delegated to an external host controller in competing solutions, greatly reducing software porting efforts and eliminating real-time processing requirements for an external host controller. the host controls the zipwireplus through a simple and well- defined software api common to all devices in the zipwire family. integrated line driver and frequency synthesizer the zipwireplus includes an integrated line driver and frequency synthesizer to provide a full dsl solu tion. the integrated line driver can drive the high line power enhanced pe rformance asymmetrical psds for payload rates of 768, 1544, 2048, and 2304 kbps in accordance with the g.shdsl standard. the frequency synthesiz er, along with the rest of the zipwireplus, supports data rates from 64 kbps to 4.6 mbps, and requires only one external crystal. this hi ghly integrated dsl solution enables oems to design and manufacture the mo st feature-rich, lowest power, and highest density dsl equipment in the industry. note: ? ? ? applications ? ? ? ? ? ? ? ? ? ?
m 28975 data sheet system overview contents figures ........................................................................................................................ .................................................ix tables ......................................................................................................................... ..................................................xi 1.0 sys t em ov er view ................................................................................................................ ........................... 1-1 1.1 intr oduc tion ................................................................................................................... ....................... 1-1 1.2 zipw ire p lus t r anscei ver/f r a m er functional sum m ary ....................................................................... 1-2 1.2.1 zipw ire p lus micropr o cess o r f u nctional s u m m a ry ............................................................... 1-3 1.2.2 zipw ire p lus d sp f u nc tional sum m ary ................................................................................ 1-3 1.2.3 zipw ire p lus g . hs func tional sum m ary ................................................................................ 1-5 1.2.4 zipw ire p lus d s l f r am er functional s u m m ary .................................................................... 1-6 1.2.5 zipw ire p lus atm phy t r a n smission c onverge n ce functiona l summ a r y . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.3 zipw ire p lus a f e f u nctional sum m ary ............................................................................................. .1 - 8 1.4 zipw ire p lus t r an sm it data path ................................................................................................. ........ 1-9 1.5 zipw ire p lus recei ve data pa th .................................................................................................. ....... 1-10 2.0 application i n terf aces ......................................................................................................... ......................... 2-1 2.1 single de vice co nfigurations ................................................................................................... ........... 2-1 2.2 multidevice c o nf igura t i o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 2-2 2.3 multipair dsl fram er confi g uration ............................................................................................. ..... 2-3 2.4 fram er transp arent m ode ........................................................................................................ ............ 2-6 2.5 zipw ire p lus t r anscei ver/f r a m er to bt8370 t1/e1 i n ter f ac e .............................................................. 2-6 2.6 dsl fram er to bt 8474 i n ter f a c e ................................................................................................. ......... 2-7 3.0 z i pwireplus clocki n g arc h itecture .............................................................................................. .............. 3-1 3.1 clocking arc h it ecture o v e r vi ew ................................................................................................. ......... 3-1 3.1.1 m28975 cl ocking a r chitect ur e im plem entation ................................................................... 3-1 3.2 htu - c cloc ki ng modes ........................................................................................................... ........... 3-5 3.2.1 plesiosync hr onous mode ....................................................................................................... 3- 5 3.2.2 plesiosync hr onous mode with ex ter n al cloc k refe re nce ..................................................... 3-6 3.2.3 synchr onou s mode ............................................................................................................... .3 - 6 3.2.3.1 synchr onous s l ave tra n sm it data cloc k ............................................................... 3-7 3.2.3.2 synchr onous master tra n sm i t d a t a c l o c k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3 clocking m o des f o r ht u-r applications .......................................................................................... .3 - 8 3.3.1 inde pende n t transm it/r eceive pcm cl oc ks ......................................................................... 3-8 3.3.2 pcm loop ti m e d clocki ng mode ........................................................................................ 3-8 4.0 z i pwireplus framer de ta il ed des cription ........................................................................................ ......... 4-1 4.1 distinguishi ng features ........................................................................................................ ................ 4-1 4.2 com m on func tions ............................................................................................................... ............... 4-3 4.2.1 data f i fo ...................................................................................................................... ........ 4-3 4.2.2 tw o-f r am e receive slip b u ff er ............................................................................................ 4-3 4.3 dsl sec tion .................................................................................................................... ..................... 4-4 4.3.1 gene ral dsl f unction ........................................................................................................... 4-4 4.3.1.1 crc gene rato r ....................................................................................................... 4-4 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential v
system overview m 28975 data sheet 4.3.1.2 scram b ler/ de scram b ler ......................................................................................... 4-4 4.3.1.3 auxiliary cha nnel .................................................................................................. 4-4 4.3.1.4 rx d s l re fer e nce p h as e measurem ent ................................................................ 4-5 4.3.2 dsl recei ver fu nctionality .................................................................................................. 4-5 4.3.2.1 dsl recei ver sync de tector (ds d ) ...................................................................... 4-5 4.3.2.2 dsl recei ver tip/ring re ve rsal detec tion .......................................................... 4-5 4.3.3 dsl tra n sm itter functiona lity .............................................................................................. 4-6 4.3.3.1 dsl tra n sm it stuf fing gene r a tor .......................................................................... 4-6 4.4 pcm sec tion .................................................................................................................... .................... 4-7 4.4.1 pcm inte rface .................................................................................................................. ...... 4-7 4.4.2 system bus tim i ng .............................................................................................................. .. 4-8 4.4.3 gene ral pcm fu nctions ....................................................................................................... 4-1 2 4.4.3.1 crc gene rato r ..................................................................................................... 4-12 4.4.3.2 inse rt/dr o p ........................................................................................................... 4-12 4.4.3.3 ove r head ha ndling .............................................................................................. 4-12 4.4.3.4 e1 gr oom i ng ........................................................................................................ 4-12 4.4.3.5 multifram e phase m easurem ent ........................................................................... 4-12 4.4.4 pcm recei ver ................................................................................................................... ... 4-13 4.4.5 pcm tra n sm itter ................................................................................................................ .4 - 1 3 4.4.5.1 pcm sync det ector .............................................................................................. 4-13 4.4.6 prim ary rate a ccess (pr a ) ................................................................................................. 4-13 4.4.6.1 distinguishi ng features ........................................................................................ 4-14 4.4.6.2 pra ove r view ..................................................................................................... 4-14 4.5 nar r ow band p o rt ................................................................................................................ ................ 4-15 4.6 atm-tc and uto p i a l e ve l 2 inter f ace .......................................................................................... 4- 15 4.7 test and di agnos tics ........................................................................................................... ............... 4-18 4.7.1 perf orm a nce m onitoring ...................................................................................................... 4-1 8 4.7.2 prbs and be r meter .......................................................................................................... 4-1 8 5.0 hardw a re i n t erfaces ............................................................................................................ ......................... 5-1 5.1 zipw ire p lu s clocks ............................................................................................................. ................ 5-1 5.2 dri v ing the cr ystal am plifier directly ......................................................................................... ....... 5-2 5.3 configura tion pins ............................................................................................................. .................. 5-2 5.4 internal 8051 com m unicatio n in terfaces ......................................................................................... .... 5-3 5.4.1 host port ra m inte rf ace ....................................................................................................... 5 -3 5.4.1.1 host port har d ware im plem entation ...................................................................... 5-3 5.4.2 host port tim i ng ............................................................................................................... .... 5-4 5.4.2.1 host port writ e cycle tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.2.2 host port rea d cycle tim i ng ................................................................................ 5-5 5.5 zipw ire p lus t r anscei ver/f r a m er to afe i n terface ............................................................................. 5-6 5.6 transm ission li ne i n ter f ace .................................................................................................... ............. 5-7 5.6.1 com p rom i se hybrid .............................................................................................................. 5-7 5.6.2 line drive r c o m p ensation ..................................................................................................... 5- 7 5.6.3 im pedance ma tching resistor s .............................................................................................. 5-8 5.6.4 transf orm e r .................................................................................................................... ....... 5-8 5.6.5 anti-alias filte rs ............................................................................................................. ....... 5-8 vi mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet system overview 5.6.6 sur g e pr otection ............................................................................................................... ...... 5-8 5.7 voltage refe re nce a n d co m p ensation ci rc uitry .................................................................................. 5 -9 5.8 test and diagnostic i n terfa ce (jta g ) ........................................................................................... ...... 5-9 6.0 pin descri p t ions ............................................................................................................... ............................. 6-1 6.1 zipw ire p lus p i n as signm e nts .................................................................................................... ......... 6-1 6.1.1 zipw ire p lus t r anscei ver/f r a m er pin assi gnm e nts ............................................................... 6-2 6.1.2 zipw ire p lus a f e pi n assignm ents ....................................................................................... 6-4 6.2 zipw ire p lus s i gna l descri ptions ................................................................................................ ......... 6-5 6.2.1 zipw ire p lus t r anscei ver/f r a m er signal de scriptions .......................................................... 6-5 6.2.2 zipw ire p lus a f e si gna l des c riptions ................................................................................ 6-10 7.0 electrical and mech anic al s p ecificati o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 7-1 7.1 specifications for the zipwir eplus t r a n scei ver/ fram er and zi pw ire p lus a f e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 recommended operatin g c o nditions .................................................................................... 7-1 7.1.2 recom m e nded power se quencing ......................................................................................... 7-2 7.1.3 abs o lute maxi m u m ratings .................................................................................................. 7-2 7.2 therm a l chara c teris t i c s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................ 7-3 7.2.1 zipw ire p lu s a f e ................................................................................................................ .. 7-3 7.2.2 zipw ire p lus t r ans cei ver/f r a m er ........................................................................................... 7-3 7.3 specifications for zi pw ire p lus tra n sceive r/ fram er only ................................................................... 7-4 7.3.1 power dissi pation .............................................................................................................. .... 7-4 7.3.2 dc cha r act eri s tics ............................................................................................................. .... 7-4 7.3.3 host port ram in te rface tim i ng .......................................................................................... 7-5 7.3.4 dsl fram er t i m i ng require m ents ........................................................................................ 7-7 7.3.5 dsl fram er s w itching c h ara c teristics .................................................................................. 7-8 7.3.6 utopia inte rf ace tim i ng ..................................................................................................... 7-9 7.4 specifications for zi pw ire p lus af e only ........................................................................................ .7 - 1 3 7.4.1 power c o nsum ption ............................................................................................................. 7 -13 7.4.2 dc cha r act eri s tics ............................................................................................................. .. 7-13 7.5 mechanical s p ecifica t i o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............ 7-15 7.5.1 the 13 x 13 m m fpbga ..................................................................................................... 7-15 7.5.2 176-pin lq fp ................................................................................................................... ... 7-16 7.5.3 48-pi n et qf p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 7-17 appe ndix a : p o w er consum ption ..................................................................................... ....................... a-1 appendix b: surf a ce m o un t a pplication note ?fpbg a pack ag e f a mi ly ............................................. b-1 b.1 pur p ose ........................................................................................................................ ......................... b-1 b.2 solde r pad ge om etry ............................................................................................................ ............... b-1 b.3 solde r stencil determ ination ................................................................................................... ............ b-3 b.4 solde r re fl ow pr ofile .......................................................................................................... ................. b-3 appendix c: surf a ce m o un t a pplication note ? elqfp pac k age f a m ily ........................................... c-1 c.1 pur p ose ........................................................................................................................ ......................... c-1 c.2 center pa d ge om etry ............................................................................................................ ............... c-1 c.3 solde r stencil determ ination ................................................................................................... ............ c-2 c.4 solde r re fl ow pr ofile .......................................................................................................... ................. c-2 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential vii
system overview m 28975 data sheet appendix d: exposed pad thin qu ad flat pac k (etq fp) ................................................................... d-1 abs t rac t ....................................................................................................................... ............................................ d-1 d.1 intr oduc tion ................................................................................................................... ...................... d-1 d.2 packa g e t h er m a l ch aracterization ............................................................................................... ....... d-2 d.2.1 heat rem oval path .............................................................................................................. .d - 2 d.2.2 therm a l lands .................................................................................................................. .... d-2 d.3 pcb desi gn ..................................................................................................................... .................... d-5 d.4 therm a l test struct ure ......................................................................................................... ............... d-6 d.4.1 test envir onm ent ............................................................................................................... ... d-6 d.4.2 therm a l test boar ds ............................................................................................................ .d - 6 d.5 packa g e t h er m a l perform ance .................................................................................................... ........ d-8 d.5.1 calculation guide lines ......................................................................................................... .d - 8 d.5.2 packa g e t h er m a l resistance ................................................................................................. d-8 d.6 solde r stencil determ ination ................................................................................................... ......... d-10 d.7 solde r re fl ow pr ofile .......................................................................................................... .............. d-10 appendix e: acronyms an d a bbr e v iations ............................................................................................. e-1 viii mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet system overview figures figure 1- 1. hi gh le ve l f unct i onal diagram ...................................................................................... ......... 1-1 figure 1- 2. zipw i r epl u s t r ansceiver/ f r am er detailed bl oc k diagram ...................................................... 1-2 figure 1- 3. zipw i r epl u s ds p detailed bloc k diagram ............................................................................. .1 - 4 figure 1- 4. g . hands h a k e block diagram .......................................................................................... .......... 1-5 figure 1- 5. d s l fram er deta iled bloc k dia g ram .................................................................................. .... 1-6 figure 1- 6. a t m ph y tc fu nctional bl ock diagram ............................................................................... 1 -7 figure 1- 7. zipw i r epl u s afe block diagram ...................................................................................... ...... 1-8 figure 1- 8. det a iled tra n sm it data path bl oc k diagram .......................................................................... .1 - 9 figure 1-9. det a iled receive data path bl oc k diagram ........................................................................... 1-10 figure 2- 1. single pair ha rdw a re configurati o n usi n g h o st port .............................................................. 2-1 figure 2-2. ma ster multipai r hardware c onfigura tion ............................................................................ ... 2-2 figure 2-3. multipair co nfiguration? pcm bu s e d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 2-4 figure 2-4. multipair conf iguration?pc m cascade ................................................................................ .2 - 5 figure 2- 5. zipw i r epl u s t r ansceiver/ f r am er to bt8370 t1 / e 1 inte rface ................................................... 2-6 figure 2-6. ds l fram er to bt 8474 inte rface diag ram ............................................................................. .. 2-7 figure 3- 1. m28975 cl oc k t r ee dist ribution ..................................................................................... ......... 3-3 figure 3- 2. ple s iosync hr on ous mode bloc k diagram ............................................................................... .. 3-5 figure 3- 3. pes i osync h r o nous mode bloc k d i agram ................................................................................ .. 3-6 figure 3- 4. sy nchr onous sl a v e t r ansm it data clock .............................................................................. ... 3-7 figure 3- 5. sy nchr onous ma s t er tra n sm it data clock ............................................................................. .. 3-7 figure 3- 6. sy nchr onous pc m lo op tim e d clocki ng mode ..................................................................... 3-8 figure 4- 1. d s l fram er deta iled bloc k dia g ram .................................................................................. .... 4-2 figure 4-2. dsl aux iliary channe l timing ....................................................................................... ........ 4-4 figure 4- 3. d s d sy nchron iza tion stat e mac h ine .................................................................................. ..... 4-5 figure 4- 4. i n t e grate d slip b u f f er and system bus inter f ac e .................................................................... .. 4-7 figure 4- 5. 1,544 k b ps syste m bus tim i ng ....................................................................................... ........ 4-8 figure 4- 6. 2,048 k b ps syste m bus tim i ng ....................................................................................... ........ 4-9 figure 4- 7. cloc k e d ge options ................................................................................................. ............... 4-10 figure 4- 8. sys t em bus clock rate greate r t h an payloa d r a te ................................................................ 4-11 figure 4- 9. i n s e rt/d r o p tim i n g diagram ......................................................................................... ......... 4-12 figure 4- 10. p r a o v e r vie w ...................................................................................................... ................ 4-15 figure 4- 11. i n tegrated o n e p o rt of rs 8228 with xd sl fra m er .............................................................. 4-17 figure 4- 12. b e r m easurem ent tim i ng ............................................................................................ ....... 4-19 figure 5- 1. di f f ere n tial crys tal am plifier co nfigura tion ....................................................................... .... 5-1 figure 5- 2. di r ect clock c onnection ............................................................................................ .............. 5-2 figure 5- 3. h o st port i n ter f ac e block dia g ra m ? host port side ............................................................... 5-3 figure 5- 4. h o st port write cycle tim i ng ....................................................................................... ........... 5-4 figure 5- 5. h o st port read cycl e tim i ng ........................................................................................ ........... 5-5 figure 5- 6. zipw i r epl u s t r anscei ver/f r am er to afe i n terfa ce .................................................................. 5- 6 figure 5- 7. d s l tra n sm ission li ne i n ter f ac e .................................................................................... ......... 5-7 figure 7- 1. h o st port write cycle tim i ng ....................................................................................... ........... 7-5 figure 7- 2. h o st port read cycl e tim i ng ........................................................................................ ........... 7-6 figure 7- 3. i nput cloc k requi r em ents ........................................................................................... ............. 7-7 figure 7- 4. i nput setup a n d h o ld re quirem ents .................................................................................. ....... 7-7 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential ix
system overview m 28975 data sheet figure 7- 5. o u tput c h aracteri s tics ............................................................................................. ................. 7-8 figure 7- 6. u t opi a tra n sm it tim i ng dia g r a m ..................................................................................... .... 7-9 figure 7-7. ut opia r ecei ve tim i ng dia g ra m ...................................................................................... .. 7-11 figure 7- 8. zipw i r epl u s afe power dissipation .................................................................................. ... 7-13 figure 7-9. pac k age ou tline for 13 x 13 fpb ga .................................................................................. .... 7-15 figure 7- 10. m echanical dra w ing 1 76-pin lqfp ................................................................................... .7 - 1 6 figure 7- 11. t o p and b o ttom vi ew of a 7x7m m 48- pin e t q fp .............................................................. 7-17 figure b - 1: recom m e nde d s m d pa d geom et ry using standar d via tec hnology ..................................... b-2 figure b - 2: recom m e nde d s m d pa d geom etry using mic r o via tec h nol ogy ......................................... b-2 figure b - 3: recom m e nde d s t encil ape r ture o p eni n g f o r the fpbg a sol d er pa d ................................... b-3 figure b - 4: t y pical tem p erature pr ofile for s u rface m o unt of fpb ga ................................................... b-4 fi gure c - 1: top m e t a l i zat i on and sol d er m a sk defi ni t i on for t h e 48l d elqfp, w h ere a = b = 7. 40 m m , c = 0. 50 m m , d = 0. 25 m m , e = 1. 00 m m , and f = 4. 70 m m ........................... c-2 figure c - 2: t y pical tem p erature pr ofile for s u rface m o un t of e l qfp ................................................... c-3 figu re d- 1: s c hem a tic representa tion o f t h e pac k a g e c o m ponents ........................................................ d-2 figure d- 2: p ackage and pc b land c o nf iguration ................................................................................ .. d-3 figure d- 3: i n ternal str u ct ur e f o r a t w o la yer pcb. ........................................................................... .... d-5 figure d- 4: i n ternal str u ct ur e f o r a si x lay e r pcb ............................................................................ ...... d-5 fi gu re d- 5: t e st per f o r m a nce st r u ct ure ( a = 1 0 0 m m , b = 100 m m , lp = 1. 40 m m , lb = 1. 60 m m ) ... d-6 figure d- 6: p ackage t h erm a l resistance as a fu nction of airfl ow vel o city for a 48 et qfp ................ d-9 figure d- 7: p ackage t h erm a l resistance as a fu nction of airfl ow vel o city for a 64 et qfp ................ d-9 figure d- 8: p ackage t h erm a l resistance as a fu nction of airfl ow vel o city for a 80 et qfp ................ d-9 figure d- 9: i r reflow p r ofi l e ................................................................................................. ................ d-10 figure d- 10: for ced co nvec tion refl ow p r ofile ................................................................................. ... d-11 x mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet system overview tables table 3- 1. cl oc king m odes ...................................................................................................... ................... 3-1 table 3- 2. zipw i r epl u s cloc ks .................................................................................................. ................. 3-4 table 5- 1. c r ysta l specifications .............................................................................................. .................. 5-1 table 5- 2. c o m m unication i n terface s ............................................................................................ ............. 5-3 table 6-1. pin list for m 2 8975 d sp/fram er?alpha be tic order .............................................................. 6-2 table 6-2. pin list for m 2 8975 afe/ line driver? a lpha be tic order ....................................................... 6-4 table 6- 3. zipw i r epl u s t r ansceive r/f r am er signal de finit i ons ................................................................. 6- 5 table 6- 5. zipw i r epl u s afe signal de sc riptions ................................................................................. ... 6-10 table 7- 1. rec o m m e nded o p erating conditi ons .................................................................................... .... 7-1 table 7- 2. a b s o lute ma xim u m ratings ............................................................................................ .......... 7-2 table 7- 3. zipw i r epl u s t r ansceive r/f r am er power dissi pa tion ................................................................. 7-4 table 7- 4. tra n sceive r/fr am er dc cha r acteris tics ............................................................................... ...... 7-4 table 7- 5. h o s t port tim i ng .................................................................................................... .................... 7-6 table 7- 6: i nput cloc k tim i ng .................................................................................................. .................. 7-7 table 7- 7: i nput setu p a n d h o ld tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............ 7-7 table 7- 8: o u t put tim i ng ....................................................................................................... ..................... 7-8 table 7- 9. ut opi a tra n sm it tim i ng ta ble ........................................................................................ ..... 7-10 table 7-10. utop ia r eceive tim i ng ta bl e ........................................................................................ .... 7-12 table 7- 11. af e dc c h aracte r istics. ............................................................................................ ............ 7-13 table a- 1: p o wer consum ption of t h e m 28975 i n idle m o de /reset stage .............................................. a-1 table a- 2: p o wer consum ption of t h e m28975 i n hd sl 2 mode at 9 kft ( 2 6 a w g ) loop .................... a-1 tabl e a- 3: power c onsum pt i on of m 28975 i n g.hsdsl m ode at 9 kft (26 aw g) loop i n annex a sym m etric mode ................................................................................................................. ....................... a-1 table a- 4: c o , a nne x a, a s ym m e tric, 9 kft 26 a w g ........................................................................... a-2 table a- 5: c o , a nne x b , a s ym m e tric, 9k ft 26 a w g ............................................................................ a-2 table b- 1: re com m e nded pa d geom etry ........................................................................................... ....... b-1 table b- 2: re com m e nde d s m t reflow p r ofile ..................................................................................... ... b-3 table d- 1: dim e nsi onal para m e ters (m m ) ........................................................................................ ........ d-4 table d- 2: s p ecification fo r a tw o-layer t e st boar d ........................................................................... .... d-6 table d- 3: s p ecification for a four-layer t e st boar d .......................................................................... ..... d-6 table d- 4: s p ecification for delco the r m a l test chi p s ......................................................................... .. d-8 table d- 5: te st cond itions .................................................................................................... ................... d - 8 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential xi
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m 28975 data sheet system overview 1.0 system overview 1.1 introduction for m o st applications, the zipwireplus chip se t can be viewed as a pair of wires: the data com e s in on one term inal unit and goes out the far-end term inal unit. figure 1-1 illustrates the zipwireplus data interfaces . the dsl auxiliary interface operates at the dsl line rate. the pcm and insert/drop interfaces operate at the pcm clock rate. the narrowband (nb) interface opera tes at the narrowband clock rate. the utopia interface operates at the utopia cl ock rate. the dsl line interfaces to the phy sical twisted pairs. figure 1-1. high level functional diagram 500182a _ 0 co r ut op ia at m clo ck di framer b dsl clo ck di hdsl au x pcm st r e a m insert/drop pcm clo ck di ut op ia at m clo ck di framer b dsl clo ck di hdsl au x pcm st r e a m insert/drop pcm clo ck di d s l li ne n a rrow band s nb clo ck di n a rrow band s nb clo ck di 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 1-1
system overview m 28975 data sheet 1.2 zipwireplus transceiver/framer functional summary figure 1-2 illustrates a detailed block diag ram of the zipwireplus transceiver/ fram er. the zipwireplus 8051 em bedded proce ssor core contains an internal boot- up ro m, execution program ra m (pra m), data storage ra m, and address decoding logic. the internal 8051 perform s transceiver startup, d s l fram e r overhead m a nagem e nt, interrupt handling, and other functions. a full-featured api com m a nd set allows th e user to configure the zipwireplus sy stem , query for status, execute loopbacks and test m odes, and dictate the program flow. figure 1-2. zipwireplus transcei ver/framer detailed block diagram 500182a_100 8051 co re ser i al pc m da t a ser i al fra m e da t a atm phy tc ds l f r am er ds p utop i a pc m afe ser i al inter f ace na rro w b a n d ho st p o rt ra m rom ser i al p o rt (2 ) ho st p o rt ra m b u s ra m zi pw i r e p l u s d sp, f r am er, a t m , u p z i pw i r epl u s afe and li ne d r i v er c opper pair 1-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet system overview 1.2.1 zipwireplus microprocessor functional summary ? the zipwireplus transceiver/fram er has a built-in 8051 m i croprocessor core with the following features: ? internal 256 by tes of direct, indirect, and bit-addressable ra m ? internal 2 kb boot ro m ? internal 8 kb data ra m ? dual-port 1 kb host interface ram ? two asy n chronous serial (rs-232) interfaces ? internal 64 kb program ra m. d u ring boot load sequence the low e r 2 k and upper 1 k are inaccessible because ram and rom, respectively, are overlaid. ? three internal tim ers/counters ? supports dual data pointers ? executes instruction cycles in four clock cycles ? operates at ~22 mhz 1.2.2 zipwireplus dsp functional summary figure 1-3 illustrates the zipwireplus transcei ver/dsp section. the transm itter receives a bit stream from the dsl fram e r and m a ps the data bits to the appropriate pulse a m plitude modulation (pa m ) sy m bols. a n optional tom linson-h a rashim a precoder (th p ) follow s the pa m m a pper. the signal is then processed by the transm it filter to achieve the desired tim e and/or frequency dom ain characteristics before being forw arded to the a n alog front end (a fe). the receiver receives serialized data from the afe device and from precoded sy m bols from the bit pum p transm itter. the precoded sy m bols feed into an echo canceller (ec) that estim ates the echo response and subtracts it from the a f e sam p les. the signal is equalized using a feed forw ard equalizer (ffe) and a decision feedback equalizer (dfe). fi nally , a trellis coded modulation (tcm) decoder recovers the inform ation bits. a n e rror predictor is used as a part of the startup algorithm and as a precoder coefficient adaptation m achine during norm a l operation. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 1-3
system overview m 28975 data sheet figure 1-3. zipwireplus dsp detailed block diagram 1-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet system overview 1.2.3 zipwireplus g.hs functional summary figure 1-4 illustrates the zipwireplus g.hs section. the g.hs block im plem ents the g . 994.1 handshaking function. the handshaking function provides a flexible m echanism for dsl transceivers to com m uni cate before exchanging signals that are specific to a particular d s l recom m e ndation or standard. the g . 994.1 standard defines the signals, m e ssages, and procedures for exchanging inform ation about the capabilities of each transceiver and for selecting com m on m odes of operation. this block im plem ents a d psk m odem that operates at a sy m bol rate of 800 sy m bols/second. this block has interfaces to the 8051 m i crocontroller, the afe, and the pll block. figure 1-4. g.handshake block diagram 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 1-5
system overview m 28975 data sheet 1.2.4 zipwireplus dsl framer functional summary figure 1-5 illustrates the zipwireplus dsl fram e r section. the dsl fram e r supports g . shdsl, h d s l2, h d s l1, ra d s l, and custom fram e structure applications. the d s l fram e r provides clock, data, and fram e form at conversion from various pcm fram e form ats to various dsl applications. the dsl fram e r supports m u lti-pair configuration such as t1 tw o loops, e1 tw o and three loops, or any point-to- m u ltipoint (p2mp) application by cascading several d s l fram e rs. the d s l fram e r provides full pcm term ination capabilities, including sy nchronization and m a nagem e nt of e1 pra and t1. a second independent pcm interface (narrowband) is provided to support m u ltiservice applica tions. the dsl rate can vary from 64 kbps to 4.640 mbps (2 x e1 + overhead), and the pcm rate can vary from 64 kbps up to 16.384 mbps (8 x e1) and any custom pcm rate and fram e form at within this range. the zipwireplus d s l fram e r can be configured to provide t1 path term ination capabilities and thereby elim inate the need for an external t1 fram e r in som e applications. in particular, the zipwireplu s d s l fram e r is capable of generation and insertion of t1 overhead in the transm it direction as well as alignm ent and checking of t1 overhead in the receive direction. figure 1-5. dsl framer detailed block diagram 500182a _005a internal s i gnal s e x ternal s i gnal s legend: tx pcm rx pcm tx nb rx nb pcm dsl narrowband rx dsl tx dsl narrowband cl ock domai n pcm clock dom a in dsl clock dom a in dslsynci dslsynco tn b c lk t n bdat t n bm f sync rnbclk rnbdat rnbm f sync dsl- aux th loa d rhaux rhm ark th a u x tp c l k tp d a t t p m f sync rpclk rpdat rpm f sync multi p a i r tx p c m fifo t hdat rhdat fr_re f _clk hxclk rnbdrop t p i n sdat t p i n sen rpdrop rp dp llclk rx pcm fifo rx nb fifo tx n b fifo nb dpll pcm dpll rpext dat pext cl k pref sync 1-6 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet system overview 1.2.5 zipwireplus atm phy transmission convergence functional summary figure 1-6 illustrates the zipwireplus atm ph y s ical lay e r (phy) transm ission convergence (tc) section. the a t m ph y supports data rates ranging from 64 kbps to 50 mbps. a utopia level 2 m u lti-phy interface connects the zipwireplus to the host switch or term inal sy stem . the atm phy perform s all cell alignm ent functions on the bit stream . this gives sy stem designers a sim p le, m odular, and low - cost architecture for supporting all uni and nni atm interfaces. note: the atm phy tc block is a single bloc k of mindspeed?s rs8228 octal tc phy device. figure 1-6. atm phy tc functional block diagram 8k hzin ones ecout ones ecin one s e cond interface host interface transmi t ut opia level 2 mi croprocessor interface s t atus and control tp c l k tp d a t t p m f sync loopback control host interface transmi t ut opia level 2 pcm i/f fr am er (line) inter f ace rpclk rpdat rpm f sync ut opia level 2 inter f ace 500182a _102 li ne transmi tter li ne receiver a t m c e l l trans mi t t e r 4-cel l fi fo 4-cel l fi fo cell a l i gnment ce ll va lid a t io n v p i /v ci s c reeni ng at m ce ll re ce ive r a t m_tx _clk a t m_tx _cla v at m _ t x _ e nb at m _ t x _ s o c a t m_tx _da t a [ 0:15] at m _ t x _ p rt y at m _ t x _addr[0:4] a t m_rx _clk a t m_rx _cla v at m _ rx_enb at m _ rx_ s o c a t m_rx _da t a [ 0:15] at m _ rx_prt y at m _ rx_addr[0:4] 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 1-7
system overview m 28975 data sheet 1.3 zipwireplus afe functional summary figure 1-7 illustrates the zipwireplus afe. the zipwireplus afe perform s the analog functions required for transm ission and reception of g.shdsl, epap, optis, or 2b1q line-coded signals. the zipwirep lus afe includes the digital-to-analog (d/a) and analog-to-digital (a/d) data c onverters, anti-aliasing and post filtering circuitry , gain control blocks, and line drivers. the zipwireplus afe serial digital interface connects to the zipwireplus transceiver/fram er. the serial interface prot ocol is proprietary. the dsp transceiver indirectly controls the afe. the afe interface consists of the line driver, im pedance-m a tching resistors, external hy brid, and transform e r. figure 1-7. z i pwirep lus afe block diagram 1-8 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet system overview 1.4 zipwireplus transmit data path figure 1-8 illustrates the input data sources available to be transm itted over the zipwireplus link. this draw ing includes all external inputs, as w e ll as internally generated data sources. note: this figure does not show loopbacks. figure 1-8. detailed transmit data path block diagram zipwirep lus afe ds l line legend : connec t e d t o a pin api co n t r o l co mma n d def a ult pat h (bold lines ) not e : dsl f a mer mux dat a on a per t i me sl ot basi s bi t pump and afe over r i des al l dat a. line driver 500182a_007 ds l framer b l oc k pr evi ous dat a prbs hdsl aux dbank2 dbank1 over head ( crc, eoc i nd, et c. ) sync wo r d 0x34, 0x35 tx pc m t x hdsl tfifo dat a prbs tnb pcm tn bfifo scr pr evi ous 0x30, 0x31 0x38, 0x39 trans c e iv er b l oc k 0x0d tx d s p c/ r t ones iso pu l s e scr 4/ 8/ 16/ 32 cont inous tnbdat in s_ d a t atm tpd a t 0x1e not e : over head and sync wor d aut omat i c al l y muxed on pr oper bi t s pcm cloc k domain dsl cloc k domain 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 1-9
system overview m 28975 data sheet 1.5 zipwireplus receive data path note: this figure does not show loopbacks. figure 1-9 illustrates the data paths received from the zipwireplus link. this draw ing includes all external inputs, as w e ll as internally generated data sources. note: this figure does not show loopbacks. figure 1-9. detailed receive data path block diagram zipwirep lus afe rx pcm ds l line prbs rx hdsl dbank3 dbank1/ 2 0x36, 0x37 legend: di scard descr descr si gnal tabl e 0x32, 0x33 rf i f o rnb pcm prbs dbank1/ 2 / 3 r n b fifo a/d 500182a_008 not e : over head and sync wor d aut omat i c al l y muxed on pr oper bi t s not e : dsl f a mer mux dat a on a per t i me sl ot basi s bi t pump and afe over r i des al l dat a. rnbdat rpdat rpextdat ds l framer b l oc k over head ( crc, eoc i nd, et c. ) hdsl aux connec t ed t o a pin a p i c ont rol c o mmand def ault pat h (bold lines ) trans c e iv er blo c k 0x3a, 0 x3b 0x1e atm pcm cloc k domain dsl cloc k domain 1-10 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet application interf aces 2.0 application interfaces this section illustrates various application configurations. each figure illustrates different interface configurations. 2.1 single device configurations figure 2-1 illustrates the configuration fo r a single device zipwireplus sy stem . figure 2-1. single pair hardware configuration using host port 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 2-1
application interf aces m 28975 data sheet 2.2 multidevice configurations figure 2-2 illustrates the hardware configuration when the host processor is connected directly to the hos t port of the zipwireplus. figure 2- 2. master multipair hardware conf iguration 2-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet application interf aces 2.3 multipair dsl framer configuration the dsl fram er pcm bus operates up to 16 mhz by cascading m u ltiple zipwireplus devices. multipair configura tion is necessary to support several applications: point-to-multipoint, t1 tran sport over tw o h d s l1 w i re pairs (bellcore standard), and e1 transport using tw o or three hdsl1 wire pairs (etsi standard). several cascading d s l fram e rs support these applications. the following pins are used in cascade m ode: dslsynci, dslsynco, pextclk, an d rpextdat. two options can be used to im plem ent m u ltipair configuration: ? pcm bused (see figure 2-3) enables the connection of an unlim ited num ber of fram e rs to receive the pcm highway interface in which each fram e r contributes and routes different tim e slots to and from the pcm highw ay . in this option, none of the fram e rs carry a com p lete pcm fram e ; therefore, pcm fram i ng term ination (pra) is not feasible. ? pcm cascade (see figure 2-4) enables transm it and receive pcm fram i ng (pra) by routing the receive pcm fram e data from dsl fram e rs 2 and 3 to dsl fram e r 1 (m aster) using the rpex td a t pin. this configuration is lim ited to three dsl fram e rs. in the transmit path direction, both confi guration options behave the same and have the same capability. the transmit pcm signal (clock, data, and sync) connects to the transmit pcm pins of each dsl framer while each framer is programmed independently to route any incoming pcm data combination to the dsl channel. in the receive path, the master frame r aligns the slaves (dsl framer 2 and dsl framer 3) receive pcm time base using the prefsync bi-directional pin. the recovered pcm clock is then provided to the slave framers using rpclk and pextclk pins. this capability enables the generation of a common receive pcm time base for all dsl framer receive channels and reliably reconstructs the pcm frame. the active dpll (typically located in the ma ster framer) is able to select any dsl frame reference (for the dpll phase de tector) using dslsynci and dslsynco pins. this allows the master to switch dsl reference sources when the selected pair becomes inactive (dsl loss-of-signal detection). 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 2-3
application interf aces m 28975 data sheet figure 2-3. multipair configuration?pcm bused 2-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet application interf aces figure 2-4. multipair configuration?pcm cascade 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 2-5
application interf aces m 28975 data sheet 2.4 framer transparent mode fram er transparent m ode w ould be required w h en the sy stem needs to support interoperability with legacy sdsl (2b1q) applications that do not use the dsl fram e r. when the dsl fram e r is configured to transparent m ode, the data passes through the fram e r w ithout adding any overhead. to configure the d s l fram e r for transparent m ode, the fram e structure param e ter in the dsl_system_config a p i (o pcode 0x06) should be set to _tra n spa ren t _fo r ma t (value 0x05). 2.5 zipwireplus transceiver/framer to bt8370 t1/e1 interface figure 2-5 illustrates one possible configur ation for the zipwireplus transceiver/ fram er to bt8370 t1/e1 interface. figure 2-5. zipwireplus transcei ver/framer to bt8370 t1/e1 interface 2-6 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet application interf aces 2.6 dsl framer to bt8474 interface figure 2-6 illustrates the connection of th e zipwireplus device to the bt8474 device when using the zipwireplus dsl fram er block. in an htu-c (central office) application, the d s l fram e r d p ll is program m e d to open loop m ode to provide the clock reference. in an htu-r (rem o te te rm inal) application, the dsl fram e r dpll is program m e d to closed loop m ode to recover the pcm clock reference from the htu-c. the dsl fram e r generates the transm it and receive m u ltifram e sy nchronization reference and feeds it to the bt8474 device. the m u ltifram e sy nchronization signals are only required in channelized applications w h ere individual tim e slots are sourced from different devices. figure 2-6 illustrates a one-port connection. figure 2-6. dsl framer to bt8474 interface diagram 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 2-7
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m 28975 data sheet z i pw ir eplus clocking ar chitectur e 3.0 zipw ireplus clocking architecture 3.1 clocking architecture overview the m28975 provides a flexible clocking architecture to support a num ber of applications defined by various standards such as g . shdsl, h d s l2, h d s l1, sd sl. table 3-1 lists the supported clocking m odes. in general, the h t u - c clocking architecture m u st support the different m odes w h ile the h t u - r clock reference is derived from the received sym bol clock. htu-c clocking m odes are described in section 3.2 w h ile h t u - r clocking m odes are described in section 3.3. table 3-1. clocking modes mode # mode name htu-c clock reference application 1 ples ios y n c h ronous loc al os c illator (free running) cl a ssi c hdsl 2 p l e s ios y n c h ronous w i t h timing referenc e network referenc e cl o ck c l assic hds l 3 sy nc hronous trans mit data c l oc k or network referenc e cl o ck ? 4 hy brid trans mit data c l oc k downs t ream is s y n c h ronous while ups tream is ples ios y n c h ronous . 3.1.1 m28975 clocking architecture implementation figure 3-1 illustrates the m28975 clock tree distribution. the on-chip clock sy nthesizer (pll) block is responsible for generating the d sp, m i croprocessor, a f e, dsl fram e r, and atm reference clocks. the zipwireplus dsl fram e r has two independent d p lls to generate pcm and n b clocks. the on-chip clock sy nthesizer can operate in free running netw ork tim ing reference, or h t u - r d s l/g . hs tim ing recovery m ode. in free running m ode, the zi pwireplus clock sy nthesizer operates at the cry s tal (or local clock) phase offset. in netw ork tim ing reference m ode, the zipwireplus clock sy nthesizer will phase-lock its tim ing to the external reference clock. the external reference clock can be sourced from ext_clk_ref pin or the internal i_tpclk signal. in h t u - r d s l/g . hs tim ing recovery m ode, the 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 3-1
z i pw ir eplus clocking ar chitectur e m 28975 data sheet zipwireplus clock sy nthesizer will phase-lock its tim ing to the far end m odem (h tu -c) via the g . hs or d s l signal. 3-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet z i pw ir eplus clocking ar chitectur e figure 3-1. m28975 clock tree distribution 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 3-3
z i pw ir eplus clocking ar chitectur e m 28975 data sheet table 3-2. zipwireplus clocks clock frequency description cry s t al 22.1184 mhz ex ternal c r y s t al or c l oc k input xtali / xtalo 22.1184 mhz cry s t al input/output xtalo_b 22.1184 mhz buffered c r y s t al output ext_clk_ref (input) 8 k h z ?18.432 mhz bidirec t ional network timing referenc e cl o ck ext_clk_ref (output) 8 khz bidirectional network timing reference clock 8 k h z in 8 k h z internal 8 k h z input deriv ed from ext_clk_ref 8 k h z out 8 k h z internal 8 k h z output from pll. deriv ed from 8 k h z (s ee figure 3-1) when htu-c or rec o v e red from dsl line when htu-r. routed to atm bloc k and ext_clk_ref output. sys_clk 43?53 mhz internal dsp system clock afe_clk sys_clk / 2 afe clock reference g.hs cloc k 12 k h z or 20 k h z g.hs c l oc k ? 12 k h z (htu-r) or 20 k h z (htu-c) baud rate 115200 baud rate that c ontrols s e rial ports 0 and 1 hxclk 64 k ?4640 k bps data rate c l oc k output 3-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet z i pw ir eplus clocking ar chitectur e 3.2 htu-c clocking modes this section describes how the various clocking m odes are targeted for h t u - c applications. 3.2.1 plesiosynchronous mode figure 3-2 illustrates the plesiosy nchronous-clocking m ode. in this m ode, the transm it pcm clock and d s l clock operate independently (w ithin appropriate ppm tolerance) and do not have any phase relationship with respect to each other. the stuffing generator is used to com p ensate for any phase differences between the pcm and d s l clock dom ains. the h t u - c locks the d s l clock to a local clock or oscillator. the transm it pcm clock (tpclk) signal can be generated by an external device such as the bt8370 (t1/e1 fram e r) or can be sourced from the pcm d p ll when operating in open loop m ode. the transm it pcm and receive pcm clocks can operate at independent rates within the appropriate ppm tolerance. t1/e1 transport applications use this m ode. note: figure 3-2 applies to both the htu-c and htu-r. figure 3-2. plesiosynchronous mode block diagram f r am er tx d i re ct i o n bit- p u mp e x te r n a l d e v i ce lo cal cl o c k dp l l ds l da t a ra te cl o c k rp cl k tp cl k rx di r e c t i o n pc m do m a i n ds l do m a i n xt a l i ht u- c an d ht u- r stu ffin g 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 3-5
z i pw ir eplus clocking ar chitectur e m 28975 data sheet 3.2.2 plesiosynchronous mode with external clock reference figure 3-3 illustrates the plesiosy nchronous m ode with external reference clock. this m ode is sim ilar to plesiosy nchronous m ode except that the h t u - c locks the d s l clock to an external reference clock, either from a network reference clock or the transm it pcm clock. if the external reference clock is sour ced from the tpclk pin, the dsl and pcm clock dom ains are sy nchronized. however, the stuffing generator is still used and is therefore a slightly different configurati on than the sy nchronous m odes described in section 3.2.3. this configuration is used when the transm it pcm clock is locked to a netw ork reference clock and the d s l clock needs to be sy nchronized to the netw ork reference clock via the transm it pcm clock. figure 3-3. pesiosynchronous mode block diagram f r am er tx d i re ct i o n bit- p u mp e x te r n a l d e v i ce lo cal cl o c k dp l l ds l da t a ra te cl o c k rp cl k tp cl k rx di r e c t i o n pc m do m a i n ds l do m a i n xt a l i ht u-c stu ffin g net w o r k re fe r e n c e c loc k (i n t erna l si gn al ) ne tw o r k ref e re nc e cl o c k clk _ re f 3.2.3 synchronous mode in the sy nchronous m ode, the d s l and pcm clock dom ains are sy nchronized. the stuffing generator is therefore disabled. the sy nchronous m ode can be achieved in two following way s : sy nchronous slave transm it d a ta clock sy nchronous master transm it d a ta clock 3-6 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet z i pw ir eplus clocking ar chitectur e 3.2.3.1 synchronous slave transmit data clock figure 3-4 illustrates the slave transm it data clock m ode. in this configuration, the m28975?s transm it pcm clock is slaved off of an external device. in this m ode, the htu-c locks the dsl clock to the transm it pcm clock (tpclk). the transm it pcm clock (tpclk) and receive pcm clock (rpc lk) are both sourced (slaved) from the tpclk input pin. the tpclk m u st be supplied from an external source. the pcm d p ll is disabled. figure 3-4. synchronous slave transmit data clock tx d i re ct i o n bit- p u mp e x te r n a l d e v i ce lo cal cl o c k f r am er rx pc m ds l da t a ra te cl o c k rp cl k tp cl k rx di r e c t i o n pc m do m a i n ds l do m a i n xt a l i clk _ re f ht u- c on l y ne tw o r k ref e re nc e cl o c k clk _ re f (i nte r nal s i ngal ) 3.2.3.2 synchronous master transmit data clock figure 3-5 illustrates the m a ster transm it data clock m ode. in this configuration, the m28975 is the pcm clock m a ster. a n y external device needs to be slaved to the m28975 clocks. the dsl clock dom ain is sy nchronized to the local oscillator or the external network reference clock. the transm it pcm clock (tpclk) and receive pcm clock (rpclk ) are then sy nchronized w ith the d s l clock using the pcm dpll. figure 3-5. synchronous master transmit data clock tx d i re ct i o n bit- p u mp at m or ex t e rn al d e vi c e lo cal cl o c k net w o r k re fe r e n c e cl o c k f r am er dp l l ds l da t a ra te cl o c k rp cl k rx di r e c t i o n pc m do m a i n ds l do m a i n xt a l i ex t _ re f ht u- c on l y 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 3-7
z i pw ir eplus clocking ar chitectur e m 28975 data sheet 3.3 clocking modes for htu-r applications this section describes how the various clocking m odes are targeted for h t u - r applications. in general, the htu-r w ill recover the dsl, pcm, and network references clocks from the incom i ng d s l line. the pcm clock can operate in looped tim ed or independent transm it/receive pcm clock m odes. the network reference clock output is optional. note: when operating as an htu-r, the devi ce can support all of the htu-c clocking schemes but the htu-c modes are not required in most applications. 3.3.1 independent transmit/receive pcm clocks the transm it pcm and receive pcm clocks can operate at independent rates within the appropriate ppm tolerance. this m ode is the sam e as the htu-c plesiosy nchronous m ode. see section 3.2.1 for details and block diagram . 3.3.2 pcm loop timed clocking mode figure 3-6 illustrates a sim p lified block diagram of the htu-r pcm loop tim ed clocking m ode. the pcm loop tim ed clock m ode takes the pcm d p ll recovered clock (rpclk) and uses it for both the transm it pcm and receive pcm directions. this m ode is applicable in stuffing and non-stuffing m odes. this configuration is sim ilar to section 3.2.3.2. figure 3-6. synchronous pcm loop timed clocking mode tx d i re ct i o n bit- p u mp at m or ex t e rn al d e vi c e lo cal cl o c k net w o r k re fe r e n c e cl o c k f r am er dp l l ds l da t a ra te cl o c k rx di r e c t i o n pc m do m a i n ds l do m a i n xt a l i clk _ re f ht u- r on l y cl k_ re f 3-8 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description 4.0 zipw ireplus framer detailed description this section provides a detailed description of the various m odules of the d s l fram e r block. figure 4-1 provides a detailed block diagram of the d s l fram e r block. 4.1 distinguishing features ? program m a ble fram e form at generator w h ich supports g . shdsl, h d s l1, h d s l2, radsl, and custom fram e form ats ? supports all legacy feat ures of bt8953a and rs8953b ? com p liant with etsi rts/tm-06008 ? o n e, tw o, or three pair t1/e1 etsi and bellcore standard application ? isdn prim ary rate access (pra) ? custom n x 64 over one, tw o, or three pairs ? asy m m e tric pcm rate and fram e form at capability ? v a rious rates of pcm clock recovery (64 kh z to 16 mh z) ? low jitter (wander) stuffing generator ? flexible stuff bit id (sbid ) m a pping, including m a jority vote decision (h d s l2 applications) ? three program m a ble pcm and d s l sy nchronization detectors (supports grouped and spread sy nc w o rd patterns) ? four program m a ble prbs/ber m e te rs to both pcm and d s l sides ? twelve program m a ble perform ance m onito ring counters (can be used as crc, bpv , or febe error counters) ? three program m a ble crc generators ? program m a ble scram b ler/descram b ler ? supports variable tim e slot size (eight, f our, tw o, or one) and therefore variable pcm custom frequency (n x 64, n x 32, n x16, and n x 8, respectively ) ? two fram e s receive pcm and nb slip buffer ? nb port with its own dpll ? utopia level 2 (8/16 bit m ode) interface and atm transm ission convergence (tc) 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-1
zipwireplus fram er detailed description m 28975 data sheet figure 4-1. dsl framer detailed block diagram 1 01083_005 tx uto p ia / at m - tc tx u t opi a i/f rx u t opi a i/f rx uto p ia / at m - tc tp bsp tp bsp rh bsp da t a tx p c m c l k syn c mf syn c rnb _t b _ rs t tp fr m_ s y n c tn b f r m _ syn c n b _ syn c nb _drop nb cl ock bb c l o c k hf clk sc l k hf clk le ge n d : d a ta pa th cl ock cont rol rx p c m c l k rp cm t b _rs t rds l r e f _ sel dp ll re f _ s e l rds l re f da t a syn c da ta da t a sy n c syn c tp map per rp bsp rp mapper tn b mapper nb dl l pc m dp l l /n tn b bsp rnb mapper dsl sync de te cto r rnb bsp t x a u to wl 1 t x a u to wl 2 r x a u t o w l2/ s l i p b u f f er2 c t rl rx a u to w l1/ s lip b u ffe r1 ctrl s t uffing generator tx fi fo 1 b r oadband tx fi fo 2 n a rrow ban d r x fi fo2 na r r o wb a n d r x fi fo1 na r r o wb a n d ext _ c l k _ r ef tp c l k tn b c l k rpcl k pe xt cl k rp drop rpdat rpm f sync pre f sync rpe x t d at r p d p llc lk ref c l k sy s_ cl k t p i n sen t p i n sdat t n bdat t n bsync rn b c lk rn bdrop rn bdat rn bsync tp d a t t p m f sync th lo ad th a u x hxcl k hxp rhaux rhm a r k rhdat dsl s y nci dsl s y nco th da t th _ r e f 4-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description 4.2 common functions 4.2.1 data fifo the d s l fram e r contains four data fifo s: inb tx_fifo, inb rx_fifo, ipcm tx _fifo , and ipcm rx _fifo . these fifo s are used to provide rate buffering between the pcm side data rate and the dsl side data rate. each fifo is capable of storing 512 bits (tw o e1 fram e s). 4.2.2 two-frame receive slip buffer in order to support channelized voice applications, the transm itter and receiver tim e base of the fram e r needs to be aligned and a receive slip buffer com p ensates any clock differences between the central office and the rem o te term inal. the receive slip buffer depth has to be tw o full fram e s (e1 or t1) in order to be able to add or drop a full fram e when necessary. the dsl fram e r has two receive slip buffers, one for each pcm port. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-3
zipwireplus fram er detailed description m 28975 data sheet 4.3 dsl section 4.3.1 general dsl function the dsl section consists of a transm itte r and receiver. the dsl transm itter fram e s the transm it pay l oad data, inserts the overhead, and scram b les the dsl data. the dsl receiver unscram bles the dsl data and rem oves the overhead. 4.3.1.1 crc generator the dsl fram e contains a program m a ble sixteenth order crl generator. crc calculation can be corrupted for debugging purposes. this m ode sim p ly inverts the crc calculation. 4.3.1.2 scrambler/ descrambler the d s l fram e r contains a program m a ble 23 tap scram b ler/descram b ler. the scram b ler/descram b ler operation can be by passed for debugging. 4.3.1.3 auxiliary channel the dsl auxiliary channel (thaux, rhaux) provides an alternate source of dsl pay l oad. this channel supports any pay l oad size and can function as an alternate source for the z-bits or any other select ed overhead. figure 4-2 illustrates the dsl auxiliary channel tim ing. the auxiliary channel interface has two operational m odes. in the first m ode, thload and rhmark signals sim p ly m a rk high during auxiliary input m ode. the second m ode generates gated clock in pins thload and rhmark during auxiliary m ode to clock the serial device directly . this m ode prevents additional glue logic in the interface between the dsl fram e r and the serial device. figure 4-2. dsl auxiliary channel timing 4-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description 4.3.1.4 rx dsl reference phase measurement while working in m u ltipair configuration, the dsl fram e r can m easure the receiving dsl phase difference between two pairs. this phase is m a inly used to determ ine the delta delay betw een tw o d s l channels in point to m u ltipoint application (can also be used for debugging or link delay m easurem ent). 4.3.2 dsl receiver functionality 4.3.2.1 dsl receiver sync detector (dsd) the d s l sy nchronization d e tector (d sd ) acquires and m a intains sy nchronization of the dsl. to support the w i de variety of fram e form ats, the d s d is designed in a flexible w a y that provides the following capabilities: ? sy nchronized to any grouped bit sy nchronization pattern up to 16 bits long ? dsl fram e size (nom inal) can be up to 2 16 (65,536) bits long ? stuff size can be tw o, four, six, or eight bits. for application w ithout the necessity for stuff bits (hdlc applicati ons), the dsd can search for the sync w o rd w ithout searching in variable fram e length, but search for fix location instead figure 4-3. dsd synchronization state machine 4.3.2.2 dsl receiver tip/ ring reversal detection in 2b1q m ode, tip/ring reversal is autom a tically detected and corrected by the dsd. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-5
zipwireplus fram er detailed description m 28975 data sheet in g . shdsl and h d s l2 applications, the tip/ring reversal cannot be detected by the d s l fram e r due to the non-sy m bol alignm ent nature of the d sp operation. in this case, the dsp detects and corrects tip/ring reversal. 4.3.3 dsl transmitter functionality 4.3.3.1 dsl transmit stuffing generator the stuffing generator sy nchronizes the d s l fram e period to the pcm fram e period by adding zero, tw o, four, six, or eight stu ff bits (zero, four in h d s l1 applications) to the dsl fram e period. the stuffing generator can be by passed for nonvariable fram e length applications and can also be used as an additional debugging tool. 4-6 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description 4.4 pcm section the pcm section (receiver and transm itter) is com posed of two m a jor blocks, the pcm m a pper and the layer 3 fram e r. the pcm m a pper functions as a form atter w h ich m a ps or extracts pcm pay l oad data into or out of the dsl channel thr ough the fifo. additionally , the m a pper can o v e rrid e th e d a ta with dbank o r g e n e rate a prbs seq u e n ce. the lay e r 3 fram er sy nchronizes to pcm fr am e or multi-fram e, extracts or inserts o v erhead data out of or into the pcm fram e, and checks for any block errors (such as crc). 4.4.1 pcm interface in pcm highway interface applications of 8e1/8t1, the dsl fram e r interface is com p liant with at&t chi and mitel st -bus interfaces up to 16 mhz. this interface enables m u ltipair configuration or any kind of pcm aggregation m ode that allow s data from different sites to be aggregated onto the sam e pcm bus. figure 4-4. integrated slip buffer and system bus interface 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-7
zipwireplus fram er detailed description m 28975 data sheet 4.4.2 system bus timing the m28975 sy stem bus can be configured in m a ny w a y s . the tpclk clock edge can be selected for sam p ling inputs or updating outputs. the tpmfsy n c can be program m e d as an input or output. the tpm fsy n c can indicate the first bit of the pcm fram e or can be offset. the sy stem bus clock rate can operate above the pay l oad rate. the rpd a t can either output idle code during the extra tim eslots, or go to high im pedance. figure 4-5 through figure 4-8 illustrate som e of the different configurations of the system bus. figure 4-5. 1,544 kbps system bus timing 4-8 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description figure 4-6. 2,048 kbps system bus timing 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-9
zipwireplus fram er detailed description m 28975 data sheet figure 4-7. clock edge options 4-10 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description figure 4-8. system bus clock rate greater than payload rate 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-11
zipwireplus fram er detailed description m 28975 data sheet 4.4.3 general pcm functions 4.4.3.1 crc generator the pcm section contains two generic crc generators functionally identical to the one located on the d s l side (see section 4.3.1.1 for m o re details). the pcm crc calculation can be corrupted for debugging purposes. this m ode sim p ly inverts the crc calculation. in addition, the crc generator can be bypassed or recalculated. any crc com putation form at can be generated. crc com putation can be enabled or disabled. any bit in the fram e can be replaced with either a 0 or 1 for crc com putation purposes. this capability enables support of any crc operation m e thod. 4.4.3.2 insert/drop an alternate pcm source feeds into the pcm form atter using tpinsen, tpin sd a t , and rpd r o p pins (see figure 4-9). figure 4-9. insert/drop timing diagram 4.4.3.3 overhead handling the pcm transm itter and pcm receiver can handle up to 24 overhead (oh) bytes. these ohs can function as sa bits, e bits, and a bits for e1 applications. they can be used to generate any in-band m a nagem e nt. note: this option requires modifying th e low-level dsl framer code. 4.4.3.4 e1 grooming to support the e1 point-to-multi-point (p2mp) application, it is necessary to groom channel a ssociated signaling (ca s ) from different sites. each rem o te site has a different pcm fram e sy nchronization that needs to be aligned at the central site. 4.4.3.5 multiframe phase measurement 4-12 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d d u ring e1 (p2mp) application, pcm multifram e phase m easurem ent betw een tpmfsy n c and rpmfsy n c pins w ith re spect to internal transm it mf sy nc (mfsync) is necessary at the rem o te site to com p ensate for m i salignm ent between different rem o te sites. this phase can then be used to internally align the dsl
m 28975 data sheet zipwireplus fram er detailed description transm it fram e to the pcm fram e boundary in each site. it can provide the value of each site to the central office and align the receive channel signaling to the receive e1 mf. 4.4.4 pcm receiver the m a jor tasks of the pcm receiver are as follows: 1. generate rx pcm tim e base aligned with the dsl reference (wl delay apart). 2. a ssem b le ongoing pcm fram e using flexible rx pcm m a pper table. major tasks of this table are to: a. assem b le rx pcm fram e from sel ectable sources: d s l pay l oad, prbs seq u e n ce, data bank 1 , 2 o r 3 , sig n a lin g tab l e (gro o m in g mo d e ), and rpex td a t input pin. b. enable ber m e teron a per tim e slot basis. c. a ssert rpd r o p pin to signify specific tss in rpd a t output. d. insert external pcm data (in rpextdat input) to the receive pcm fram e . used in m u ltipair configuration. 3. generate receive user interface sync signals such as rpmfsync and prefsync (m ultipair configuration pcm tim e-base sy nchronization). 4. sy nchronize w ith any lay e r 3 fram e/mf. 5. check crc (selectable) and com putes crc on the final ongoing fram e . 6. extract overhead bits. 7. enable override of each overhead bit by the mpu. 4.4.5 pcm transmitter the m a jor tasks of the pcm transm itter are to: 1. generate transm it pcm tim e base aligned with the incom i ng fram e /m ultifram e sy nchronization. 2. map pcm fram e to the tx _fifo using tx pcm mapper table. 3. enable ber m e ter on a per tim e slot basis. 4. inserts alternate pcm channel, using tpin sd a t , tpin sen pins. 5. sy nchronizes w ith any lay e r 3 fram e/mf. 6. check crc (selectable) and com pute crc on the final ongoing fram e . 7. extract overhead bits. 8. enable override of each overhead bit by the mpu. 4.4.5.1 pcm sync detector the sy nc d e tector can sy nchronize to any sy nc pattern, grouped or spread, up to 16 bits long. this capability allows the dsl fram er to sy nchronize to e1, t1, or any other fram e . this requires m odify ing the low - level d s l fram e r code. 4.4.6 primary rate access (pra) this section describes the prim ar y rate access (pra) feature. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-13
zipwireplus fram er detailed description m 28975 data sheet 4.4.6.1 distingui shing features the follow i ng provides a list of the pra soft ware features. the list is broken into the zipwireplus and host processor responsibilities. the software can term inate and insert the pra functionality in both transm it and receive direction. zipwireplus responsibilities ? align e1 frame in dsl frame ? transmit pcm multiframe self-alignment (or use external sync reference) ? output 2ms multiframe in receive direction ? automatic crc detection and insertion ? automatic crc-4 error indication bits (e bits) ? transmit remote alarm indication bits (a bits) pattern ? process spare bits (sa4, sa5, s a6, sa7, sa8) up to message level host processor responsibilities ? optionally process overhead bits; a-bits, e-bits, spare bits (sa4, sa5, sa6, sa7, sa8) messages, etc. 4.4.6.2 pra overview figure 4-10 illustrates the pra data path and term inology . the pra functionality m onitors and m a nipulates the overhead bits found in tim eslot 0 on an e1 fram e including crc-4, e-bits, a-bits, and spare (s a) bits. in addition, the pra block can either autom a tically lock onto the incom i ng m u ltifram e boundary or accept the m u ltifram e from an external source. the pra functionality can be perform ed in both the transm it and receive directions. the transm it direction is defined as the data path from the pcm interface towards the dsl interface. the receive direction is defined as the data path from the dsl interface towards the pcm interface. each direction consists of a m onitor and generator block. the pra functionality is identical in each direction, but each direction is independently controlled. in general, there are three possible w a y s to control the various overhead bits: transparent, autom a tic, and m a nual. refer to each overhead bit definition to determ ine w h ich m odes apply . ? transparent?the generator block outputs the overhead bits unaltered from the m onitor block. ? autom a tic?the generator block will autom a tically determ ine and output the appropriate overhead bits value. the overhead bits are updated every m u ltifram e sync. ? manual?the generator block outputs the overhead bits based on an a p i com m a nd received from the host processor. the generator block will continuously output the new value starting on the subsequent m u ltifram e sy nc. 4-14 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description figure 4-10. pra overview 4.5 narrowband port for sim u ltaneous transport of voice and data applications w ith a glueless solution, a secondary port is included to transm it and receive the narrowband (nb) data stream (usually used for voice). this port has all the flexibility of a pcm port but does not have the auxiliary channel and signaling table. the narrowband channel data stream m u st be sy nchronized w ith the pcm data stream . limitations 1. n a rrow b and clock m u st be sy nchronized w ith the pcm clock. this im plies the sam e frequency offset. 2. n a rrow b and cannot operate independently , requires pcm 3. n a rrow b and only supports n x 64k operation (i-bit = 0). 4.6 atm-tc and utopia level 2 interface a n a t m-tc (transm i ssion convergence) and u t o p ia level 2 (or level 1 as an option) interface are fully supported by th e dsl fram e r, com p liant with atm forum standards. this block is a slice of one port out of the octal a t m-tc ph y device (rs8228). see figure 1-1. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-15
zipwireplus fram er detailed description m 28975 data sheet i utopia level 2 interface o phy cell to utopia interface o 50 mh z m a xim u m clock rate o 8/16 data path interface o c om patible with utopia level 1 i cell alignm ent fram i ng section o atm cell interface support for: circuit-based phy sical lay e r cell-based phy sical lay e r o passes or rejects idle cells or selected cells based on header register configuration o recovers cell alignm ent from hec o perform s single-bit hec error correction and m u ltiple-bit detection o g e nerates cell status bits, cell counts, and error counts o reads all data from the utopia fifo o inserts headers and generates h e c o inserts idle cells when no traffic is ready i counter/status inform ation o o n e-second status latching o o n e-second counter latching 4-16 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description figure 4-11. integrated one port of rs8228 with xdsl framer 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-17
zipwireplus fram er detailed description m 28975 data sheet 4.7 test and diagnostics 4.7.1 performance monitoring the d s l fram e r supports up to tw elve perform ance m onitoring counters, divided equally into three sections. each perform ance-m onitoring counter can function as a crc error counter for the severe error second (ses) indicator, far end block error (febe) counter, bipolar violation (bpv) error counter, or any othe r necessary perform ance indicator counter. the receive dsl, receive pcm and tran sm it pcm support up to four perform ance m onitoring counters. 4.7.2 prbs and ber meter the d s l fram e r has four prbs/ber m e ter m odules supporting ber m easurem ent tow a rds the d s l, pcm, and n b sides. it can operate independently . the follow i ng description focuses on the pcm port; how ever, the sam e description applies to the n b port. tp_prbs (tn b _prbs) and rp_ber (rn b _b er) function as ber m e ters towards the d s l side. the rp_prbs and tp_ber f unction as ber m e ters towards the pcm side. the prbs sequence can override tpd a t and rpd a t on a per tim e slot basis, and achieve any fram e d or unfram e d test pattern exam ination. the prbs pattern is program m a ble and selected for both rp_b er and tp_ber by prbs_ta p _[2:0] registers, indicating up to 23 rd -order prbs (tap[ 23:0]): exam ple: ? for a prbs pattern of 2 15 ? 1, the poly nom ial is x 15 + x 14 + 1. ? for a prbs pattern of 2 23 ? 1, the poly nom ial is x 23 + x 18 + 1. ? for a qrss 2 20 ? 1 pattern (poly nom ial ? x 20 + x 17 + 1), 14-bit 0 suppression is im plem ented. the tp_ber and rp_ber sequence can be inverted. the constant value per tim e slot basis can override tser and rser instead of prbs. the mpu configures ber_scale to specify the test m easurem ent interval from a range of 2 21 ? 2 31 bit length. figure 4-12 illustrates the ber m easurem ent tim ing. 4-18 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet zipwireplus fram er detailed description figure 4-12. ber measurement t i ming ber rst ber sync ber meter ber intr qualification phase measurement phase ber result ready 500015_032 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 4-19
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m 28975 data sheet hardware interf aces 5.0 hardware interfaces 5.1 zipwireplus clocks the zipwireplus cry s tal am plifier provides the pll based clock sy nthesizer w ith a stable reference. the zipwireplus can ope rate with either a crystal connected directly to the cry s tal am plifier input or w ith an external clock driving the cry s tal am plifier input. the zipwireplus provides the x t a l o _ b output (w hich is a buffered output from the cry s tal am plifier) that can be used to drive the cry s tal am plifier input of other zipwireplus devices. this allows a m u ltiport sy stem to use only one cry s tal. figure 5-1 illustrates the high perform ance differential cry s tal am plifier. figure 5-1. differential crystal amplifier configuration + - xt al i xt al o table 5-1. crystal specifications parameter value nominal frequenc y 22.1184 mhz frequenc y toleranc e at 25 c 10 ppm temperature frequenc y stability w max esr 25 ? 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 5-1
hardware interf aces m 28975 data sheet general note: indiv i dual frequenc y toleranc e, temperature frequenc y s t ability , and aging requirements c an v a ry as long as the total toleranc e is les s than 32 ppm. 5.2 driving the crystal amplifier directly figure 5-2 illustrates how to drive the cry s ta l am plifier directly . unlike in previous designs, driving an external clock into the x t a l i input alone is not sufficient. y ou m u st drive the x t a l i input from an external clock and bias the x t a l o input w ith a resistive divider from 3.3 v to ground. the x t a l o pin should be biased at 1.65 v (vddo/2 ) . two 1 k ? resistors are adequate for this purpose. figure 5-2. direct clock connection + - xt al i xt al o + 3 .3 v 1 k 1 k c l oc k in put 3. 3 v lev e l to p l l x t a l o_ b 5.3 configuration pins the bo o t pin determ ines the start up operation m ode. 0 = dow nload the program from the serial port. 1 = dow nload the program from the host port. 5-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet hardware interf aces 5.4 internal 8051 communication interfaces table 5-2 lists the interfaces to com m unicate with external devices. table 5-2. communication interfaces interface description host port ram interface used by an embedded host processor to send api co mmands to the zipwireplus system. the hos t port ram us es a mailbox protoc ol to pas s the api parameters . rs-232 serial interfac e us ed by an ex ternal hos t proc es s o r (pc or terminal) to s end api c o mmands to the zi p w i r e p l u s syste m . 5.4.1 host port ram interface the host port ram interface is connected to a host processor. the host port ram functions as a sim p le m e m o ry device. the details of the h o st port ra m protocol is described in the m28975 zipwireplus g . shdsl transceiver with embedded micropro cessor programmer reference manual . 5.4.1.1 host port hardware implementation figure 5-3 illustrates the host port interf ace. the dual port ram is the sy nchronous ty pe. a ll tim ing is w ith respect to the external h p _clk input signal. figure 5-3. host port interface block diagram?host port side 1 k x 8 dual port ram address decoder address decoder 8051 core int hp_dat hp_adr hp_int data hp_adr address 101083_119 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 5-3
hardware interf aces m 28975 data sheet 5.4.2 host port timing 5.4.2.1 host port write cycle timing figure 5-4 illustrates the tim ing of a host por t write cy cle. a write cy cle is initiated by bringing both the host port chip select (h p_cs) and the w r ite enable (h p_we) low prior to the rising edge of the host port clock (h p_clk ) . the host port w r ite address (h p_a d r ) and data (h p_d a t ) m u st also be set up prior to the sam e clock edge. data is written to the ram on the ri sing edge of hp_clk. a new write cy cle m a y be perform ed every host port clock cy cle for m a xim u m throughput. write cy cles term inate when either the chip select or the write enable is deasserted. a write cy cle m a y stretch over m u ltiple hp_clk clock cy cles as long as all hold tim es are m e t on the last clock cy cle before w r ite term ination. care should be taken to raise the chip select and/or the write enable prior to rem oving the address and data so that invalid data is not unintentionally written to the host port ram. figure 5- 4. host p o rt write cycle t iming 5-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet hardware interf aces 5.4.2.2 host port read cycle timing figure 5-5 illustrates the tim ing of a host po rt, read cy cle. a host port read cy cle is initiated by setting the host port chip select (hp_cs) low while keeping the host port write strobe (hp_we) high prior to th e positive edge of the host port clock (h p_clk ) . the host port address (h p_a d r ) m u st be set up prior to this sam e clock edge. the address is latched on the rising edge of hp_clk. after the address settles internally, data becom e s available at the output of the ram. to access the data, the host port output enable (h p_o e ) and the host port chip select m u st both be held low . a read cy cle is term inated by bringing the host port chip select high. figure 5-5. host port read cycle timing 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 5-5
hardware interf aces m 28975 data sheet 5.5 zipwireplus transceiver/framer to afe interface figure 5-6 illustrates the zipwireplus tran sceiver/fram e r to afe interface. the two devices m u st be connected as show n. figure 5-6. z i pwirep lus t r ansceiver/framer to afe interface 5-6 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet hardware interf aces 5.6 transmission line interface figure 5-7 illustrates a block diagram of the dsl transm ission line interface. the dsl interface consists of the continuous tim e filter, line drive feedback resistors, im pedance m a tching resistors, com p rom i se hy brid, transform e r, and surge protection. a ll signals are differential pairs. o n ly n p o - ty pe capacitors should be used in the dsl transm ission line interface except for the surge protection blocks. the npo capacitors are selected because of their high degree of linearity characteristics. all capacitors should have a tolerance of 5% w h ile the resistors should have a tolerance of 1%. figure 5- 7. dsl t r ansmission l i ne interf ace 5.6.1 compromise hybrid the purpose of the com p rom i se hy brid is to m odel the im pedance of the transm ission line. this m odel generates an approxim a tion of the transm itted signal?s echo. the echo replica is then subtracted from the signal on the line transform e r to generate a first-order approxim a tion of the receive d signal. although the m28975 contains a digital echo canceller (ec), the hy brid is needed to reduce the signal-level input to the a n alog-to-d igital converter (a d c ). this elim inates a d c overflow on short loops and increases the resolution of the digitized received signal for better digital signal processing perform ance. 5.6.2 line driver compensation the ld _ph / ld _pl and ld _mh / ld _ml signal pairs require that capacitors be placed between them . the ldop/ldaop and ldon/ldaon signal pairs require 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 5-7
hardware interf aces m 28975 data sheet that inductors be placed between them . these com ponents should be placed as close as possible to the device. 5.6.3 impedance matching resistors im pedance m a tching resistors are placed in the transm it path so the output im pedance of the line interface m o re closely m a tches the im pedance of the transm ission line and load. this m a xim i zes the power transferre d to the receiver on the other end of the line. the load is assum e d to be 135 ? . 5.6.4 transformer the line transform e r provides d c isolati on from the transm ission line by creating a high-pass filter. the winding ratio of the tran sform e r m u st be 2.0:1 (line side:circuit side) to generate the appropriate voltage level on the line. the prim ary inductance (l) of the line side transform e r is a very critical param e ter. if the inductance is too high, the cutoff frequency of the filter will be too low and the m28975 echo canceller and equalizer will not be able to cancel out the low frequency com ponents of the echo and inter-sym bol interference (isi). if l is too low, part of the inform ation in the signal will be filtered out, thereby decr easing the signal-to-noise (snr) ratio. in addition, the line transform e r m u st m eet cer tain return loss requirem e nts to m a xim i ze system perform ance. 5.6.5 anti-alias filters anti-aliasing filters are needed to filter out high frequencies that would be aliased back into the passband as noise. these filters are m a de of all passive com ponents. the cutoff frequency (f c ) is designed to be as low as possible to achieve m a xim u m attenuation of aliasing frequencies without filtering out the desired signal. 5.6.6 surge protection mindspeed uses the sidactor ? , fuses, and diodes for surge protection on our ev m. teccor electronics (http://www.teccor.com ) has an application note ( digital line card circuit protection ) that is useful in designing surge protection. 5-8 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet hardware interf aces 5.7 voltage reference and compensation circuitry com p ensation capacitors m u st be connected betw een all m28975 voltage reference pins and analog ground. in addition to com p ensation capacitors, external passive com ponents are needed to set the bias current used in the m28975. refer to the latest m28975 ev m schem a tics for these com ponents. 5.8 test and diagnostic interface (jtag) the test and diagnostic interface com p rises a test access port and two serial test ports (stp). the test access port conform s to ieee std. 1149.1-1993 ( i eee standard test access port and boundary scan architecture) . also referred to as the joint test action group (jtag), this interface provides direct serial access to each of the transceiver' s i/o pins. this capability can be used during an in-circuit board test to increase the testability and reduce the cost of the in-circuit test process. the serial test ports function as a r eal-tim e virtual probe for looking at the transceiver' s internal signals. a m a jority of the receiver' s signal path is accessible through these outputs. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 5-9
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m 28975 data sheet pin descr i ptions 6.0 pin descriptions the zipwireplus m28975 solution is available in a tw o-device chip set. the zipwireplus transceiver/fram er/microprocessor is packaged in one device and is m a rked as the cx 28945. the zipwireplus a f e/line d r iver is packaged in a separate device and is m a rked as the cx 28927. the zipwireplus transceiver/fram er is available in two package options. the 13 x 13 m m fpbg a option is targeted for high density w h ile the 176-pin lq fp is targeted for ease of m a nufacturability . the zipwireplus afe/line driver is available in a 48-pin etq fp. 6.1 zipwireplus pin assignments this section provides the pin assignm ents for the zipwireplus devices. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 6-1
pin descr i ptions m 28975 data sheet 6.1.1 zipwireplus transceiver/framer pin assignments table 6-1 lists the 13 13 m m fine pitch ball grid array (fpbg a ) and 176-pin low quad flat pack (lq fp) pin assignm ents. table 6-1. pin list for m28975 dsp/framer?alphabetic order lqfp pi n number fpbga pin number si gnal name 72 p9 afe_clk 70 n10 afe_ctrl_data 69 m9 afe_rst 78 n12 afe_rx_ser1 77 m11 afe_rx_ser2 68 p8 afe_rx_sync 76 p10 nc1 71 r8 nc2 62 r7 afe_tx_ser1 61 p6 afe_tx_ser2 65 p7 afe_tx_sync 153 b9 atm_rx_addr0 152 d8 atm_rx_addr1 151 c9 atm_rx_addr2 150 a9 atm_rx_addr3 146 a10 atm_rx_addr4 145 b11 atm_rx_clav 140 d11 atm_rx_clk 1 a 1 atm_rx_data0 176 a2 atm_rx_data1 165 d5 atm_rx_data10 162 c5 atm_rx_data11 161 d6 atm_rx_data12 160 b7 atm_rx_data13 159 a8 atm_rx_data14 158 c6 atm_rx_data15 175 b3 atm_rx_data2 174 a3 atm_rx_data3 173 a4 atm_rx_data4 lqfp pi n number cabg a pin number si gnal name 172 b4 atm_rx_data5 171 a5 atm_rx_data6 170 c3 atm_rx_data7 167 b5 atm_rx_data8 166 c4 atm_rx_data9 143 c11 atm_rx_enb 157 d7 atm_rx_prty 154 c8 atm_rx_soc 10 d2 atm_tx_addr0 7 d 3 atm_tx_addr1 6 d 1 atm_tx_addr2 5 c 2 atm_tx_addr3 4 c 1 atm_tx_addr4 39 l1 atm_tx_clav 2 b 2 atm_tx_clk 38 n3 atm_tx_data0 35 l2 atm_tx_data1 20 h4 atm_tx_data10 1 9 g 3 atm_tx_data11 18 g1 atm_tx_data12 17 f2 atm_tx_data13 16 g4 atm_tx_data14 13 e2 atm_tx_data15 32 k2 atm_tx_data2 29 k4 atm_tx_data3 28 j2 atm_tx_data4 27 h1 atm_tx_data5 26 k3 atm_tx_data6 25 j4 atm_tx_data7 lqfp pi n number fpbga pin number si gnal name 24 h2 atm_tx_data8 21 g2 atm_tx_data9 3 b 1 atm_tx_enb 12 f4 atm_tx_prty 11 e3 atm_tx_soc 34 m3 boot 42 n1 test_ad0 41 m1 test_ad1 40 m2 test_ad2 134 b14 dslsynci 129 d15 dslsynco 33 l4 ext_clk_ref 8, 15, 22, 30, 36, 44, 58, 66, 75, 79, 97, 103, 111, 120, 124, 141, 147, 155, 164, 168, 48 p1, r3, e4, a11, c7, a6, h3, k1, n8, p11, l15, g13, f15, f3, l3, r6, r9, k13, f14, c10, b6 gnd 100 k12 hp_adr0 99 l13 hp_adr1 96 l12 hp_adr2 95 m13 hp_adr3 6-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet pin descr i ptions lqfp pi n number cabg a pin number si gnal name 94 m15 hp_adr4 93 n14 hp_adr5 92 n15 hp_adr6 91 p15 hp_adr7 85 r12 hp_adr8 84 p12 hp_adr9 64 m8 hp_clk 101 l14 hp_cs 89 r15 hp_dat0 88 r14 hp_dat1 87 p13 hp_dat2 86 r13 hp_dat3 83 r11 hp_dat4 82 n13 hp_dat5 81 m12 hp_dat6 73 m10 hp_dat7 90 p14 hp_int 105 k14 hp_oe 1 0 2 k 1 5 hp_we 149 b10 p12_rxd1 144 d10 p13_txd1 130 c15 p30_rxd0 128 d14 p31_txd0 139 c12 pextclk 126 c13 prefsync 133 a15 rhaux 132 b15 rhmark 109 j1 4 rnbclk 107 j1 3 rnbdat 106 j1 5 rnbdrop 108 h12 rnbsync 122 d13 rpclk lqfp pi n number cabg a pin number si gnal name 118 e13 rpdat 116 g14 rpdpllclk 117 f12 rpdrop 138 a12 rpextdat 121 e12 rpmfsync 63 n7 rst 55 n5 tck 51 n4 tdi 54 p4 tdo 5 7 p 5 test_e 6 0 m 7 testmode 1 3 5 a 1 4 thaux 1 3 1 c 1 4 thload 56 m6 tms 1 1 4 f 1 3 tnbclk 110 h13 tnbdat 113 g12 tnbsync 137 b13 tpclk 1 3 6 a 1 3 tpdat 127 e15 tpinsdat 115 h15 tpinsen 123 e14 tpmfsync 52 m5 trst 14, 31, 59, 74, 104, 119, 148, 163, 43 f1, j1, n6, n11, j 12, g15, d9, a7, n2 vdd (1.8 v) lqfp pi n number cabg a pin number si gnal name 9, 23, 37, 53, 67, 80, 98, 112, 125, 142, 156, 169, 47 e1, b12, b8, d4, j3 , m4, r5, n9, r10, r2, m14, h14, d12 vddo (3.3 v) 50 r4 vgnn 4 5 r 1 xtali 46 p2 xtalo 49 p3 xtalo_b 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 6-3
pin descr i ptions m 28975 data sheet 6.1.2 zipwireplus afe pin assignments the zipwireplus a f e/line d r iver is packag ed as a 48-pin exposed thin q u ad flat pack (etq fp). the pin list is show n in table 6-2. table 6-2. pin list for m28975 afe/line driver?alphabetic order etqfp si gnal name 2 a 1 2 g n d 43 a12gnd 10 a33gnd 12 a33gnd 35 afe_clk 31 afe_ctrl_data 36 afe_rst 26 afe_rx_ser1 25 afe_rx_ser2 27 afe_rx_sync 29 afe_tx_ser1 30 afe_tx_ser2 28 afe_tx_sync 9 a v b i a s 32 dgnd 40 ld_mh 39 ld_ml 46 ld_ph 47 ld_pl 42 ldaon 44 ldaop 48 ldon 1 l d o p 24 no c onnec t 37 no c onnec t 8 r b i a s 4 r c d r v n 5 r c d r v p 34 scan_en etqfp si gnal name 3 v a 1 2 41 va12 45 va12 11 va33 13 va33 38 va33 16 vbgn 17 vbgp 14 vcmi 15 vcmo 23 vhn 22 vhp 33 vd33 1 8 v r n r x 6 v r n t x 19 vrprx 7 v r p t x 21 vxn 20 vxp 6-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet pin descr i ptions 6.2 zipwireplus signal descriptions this section provides the signal descripti ons for both the zipwireplus transceiver/ fram er and zipwireplus af e/line d r iver devices. 6.2.1 zipwireplus transceiver/framer signal descriptions table 6-3 lists the zipwireplus transcei ver/fram er signal (pin) descriptions. table 6-3. zipwireplus transcei ver/framer signal definitions signal name i/o pu/ pd (1 ) description power and ground vdd (vcore) dsp core voltage ? ? dedic a ted s upply pins powering the dsp c o re. mus t be c onnec ted to +1.8 v. vdd0 (vio) i/o voltage ? ? dedic a ted s upply pins powering the i/o. mus t be c onnec ted to +3.3 v. vgnn (vesd) 5 v esd protection ? ? dedic a ted s upply pins us ed to bias input protec tion diodes . if interfac ing to other 5 v-powered dev ic es , c onnec t vgnn to +5 v; otherwis e c onnec t to +3.3 v. gnd ground ? ? common ground for zipwireplus device. clocks x t a l i c r y s t a l i n p u t i ? cry s t al = 22.1184 mhz 3.3 v input lev el. x t a l o c r y s t a l o u t p u t o ? connec tion point for the c r y s t al. xtalo_b cry s t al cloc k out o ? buffered c r y s t al os c illator output, 22.1184 mhz . ext_clk_ref referenc e cloc k i/ o ? 8 k h z referenc e c l oc k input or output. pcm interface rpclk receive p c m cl o ck o ? clocks the pcm receive outputs: rpdat, rpmsync, and rpdrop. normally deriv ed by the internal c l oc k rec o v e ry (dpll). can be derived from pextclk or tpclk. pextclk pcm external clock i (2 ) optionally s ourc e s the rpclk or tpclk or both rpclk and tpclk. rpdpllclk rx pcm dpll clock o ? dpll c l oc k output. this output c an be us ed as a c l oc k s y n thes iz er when the dpll is not being us ed for rec e iv e c l oc k rec o v e ry . alternately , trans mit c l oc k when operating as s e rial atm interfac e. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 6-5
pin descr i ptions m 28975 data sheet signal name i/o pu/ pd (1 ) description rpdat rec e iv e pcm data o ? during s pec ified time s l ots , data is c l oc k ed out by rpclk. this pin c an be optionally three-s t ated during inac tiv e time s l ots or when dsl framer is by pas s ed. alternately , rec e iv es data when operating as s e rial atm interfac e. rpextdat receive p c m external data i (2 ) used in multipair configuration, when receive p c m data from all channels needs to be routed through the master framer for p c m layer framing and overhead handling, like e1 p r a , c r c calculation, etc. a l ternately, transmit start of cell when operating as serial a t m interface. rpmfsync receive p c m multiframe sync o ? a c tive high output from the r eceive time base. optionally, programmed to mark either frame or multi-frame boundaries during framed application. a l te rnately, receive start of cell when operating as serial a t m interface. r p d r o p d r o p i n d i c a t o r o ? a c tive high output indicates when specific receive p c m time slots are present on rp da t. time slot size can be one, two, four, or eight bits long. this pin also controls the three-state output enable of rpdat in multipair configuration. prefsync receive p c m reference s y nc i/ o ? used in multi-p a ir configuration. when configured as a master, this output is the internal receive p c m time base reset which aligns the receive p c m time b ase of each slave to the master. when slave mode is selected, this signal is an rx p c m reset input (default). tpclk transmit p c m cl o ck i (2 ) normally samples the pcm transmit inputs: tpdat, tp ms y n c , and tp ins d a t on the falling edge and clocks out tpinsen on the rising edge. the edge transition is selectable. tpdat transmit p c m data i (2 ) during s pec ified time s l ots , data is s a mpled by a s e lec t ed c l oc k source (tpclk, pextclk or dpll recovery clock). tpmfsync transmit p c m multi-frame s y nc i/ o (4 ) this input resets the transmit pcm time base during framed application and is ignored in unframed mode. this signal is internally delayed by a programmable bit and frame offset to coincide with tpdat bit 0, fr ame 0. may be programmed to mark either frame or multi-frame boundaries. tpinsdat transmit p c m insert data i ? alternate s ourc e of pcm trans mits s e rial data. tpinsdat replac es tpdat when tpinsen is ac tiv e . alternately , trans mits data when operating as s e rial atm interfac e. tpinsen transmit p c m insert enable o ? active high output indicates when specific tpinsdat time slots are sampled. a l ternately, functions as receive clock when operating as serial a t m interface. narrowband interface tnbdat trans mit nb data i (2 ) during s pec ified time s l ots , a s e lec t ed c l oc k s ourc e (tnbclk, pextclk, or dpll recovered clock) samples data. tnbclk trans mit nb c l oc k i (2 ) normally, samples the nb trans mits inputs: tnbdat, tnbsync on the falling edge. edge trans ition is s e lec t able. 6-6 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet pin descr i ptions signal name i/o pu/ pd (1 ) description tnbsync 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 6-7 transmit nb multi frame sy nc i/ o (4 ) when configured as an input, this signal resets the transmit nb time base during framed application and is ignored in unframed mode. this signal is internally delayed by a programmable bit and a frame offset to coincide with tnbdat bit 0 frame 0. optionally programmed to mark either frame or multiframe boundaries. when configured as an output, this signal is active high for internal transmit nb mf sync. rnbdat rec e iv e nb data o ? during s pec ified time s l ots , data is c l oc k ed out by rnbclk. this pin c an be optionally three-s t ated during inac tiv e times l ots or when the dsl framer is by pas s ed. rnbclk receive nb clock o ? clocks the pcm receive outputs: rpdat, rphsync, and rpdrop. normally deriv ed by the internal c l oc k rec o v e ry (dpll). can be derived by pextclk or tnbclk. rnbsync receive nb multiframe sync o ? a c tive high output from the receive timebase. optionally, programmed to mark either frame or multiframe boundaries during framed application. rnbdrop receive nb data drop indicator o ? a c tive high output indicates when specific receive nb time slots are present on rnb da t. time slot size can be one, two, four, or eight bits long. this pin also controls the three-state output enable of rnbdat. used when more than one nb port is connected to the nb system bus. utopia interface atm_rx_addr[0? 4] ? i (2 ) functions as the address of the p h y device being selected for reception. address 11111 (31 decimal) indicates a null phy port. atm_rx_clav ? o ? indic a tes a fifo empty c ondition or c e ll av ailable c ondition. atm_rx_data[0? 15] ? i (2 ) functions as the address of the p h y device being selected for reception. address 11111 (31 decimal) indicates a null phy port. atm_rx_clav ? o ? indic a tes a fifo empty c ondition or c e ll av ailable c ondition. atm_rx_data[0? 15] ? o ? receives data output to the a t m layer. a t m _ r x _ e n b ? i (3 ) enables data reception when asserted low. a t m _ r x _ c l k ? i (2 ) clocks atm_rx_data on the falling edge. a t m _ r x _ p r t y ? o ? this pin is the parity calculated over the atm_rx_data bus. parity can be checked over atm_rx_data [0?7] or atm_rx_data [8?15]. this pin c an repres ent either ev en or odd parity . a t m _ r x _ s o c ? o ? indicates the first byte of valid cell data transmitted when asserted high. atm_tx_addr[0? 4] ? i (2 func tions as the addres s of the phy dev ic e being s e lec t ed for trans mis s i on. addres s 11111 (31 dec imal) indic a tes a null phy port.
pin descr i ptions m 28975 data sheet signal name i/o pu/ pd (1 ) description a t m _ t x _ c l a v ? o ? indic a tes a fifo full c ondition or c e ll av ailable c ondition. atm_tx_data[0? 15] ? i (2 ) trans mits data from the atm lay e r. a t m _ t x _ e n b ? i (3 ) enables data transmission when asserted low. a t m _ t x _ c l k ? i (2 ) us ed to s a mple atm_tx_data on the falling edge. a t m _ t x _ p r t y ? i (2 ) this pin is the parity calculated over the atm_tx_data bus. parity can be checked over atm_tx_data [0?7] or atm_tx_data [8?15]. this pin c an repres ent either ev en or odd parity . a t m _ t x _ s o c ? i (2 ) indic a tes the firs t by te of v a lid c e ll data trans mitted when as s e rted high. hdsl interface rhaux receive auxiliary data o ? after descrambling, rhdat is provided as an aux iliary channel and c l oc k ed out by hxclk. rhmark receive auxiliary data mark o ? active high output indicates when specific ds l time slots are present on rha ux . optionally, this output provides gated hxclk ins t e a d . thaux transmit auxiliary data i (2 ) a l ternate source of ds l transmit data. taux is mapped into selected ds l time slots when thloa d is active. thload transmit auxiliary data load o ? active high output indicates when specific dsl time slots will be replaced by tha u x . optionally, this pin provides gated hxclk ins t e a d . dslsynci dsl reference sync in i (2 ) used in multipair configuration to select the internal rdsl_ref_sel for dpll phase reference and rh_bsp reset. alternatively, can be used as atm one second input. dslsynco dsl reference sync out o ? the selected dsl sync for dpll reference and rh_bsp reset is output in dslsynco to allow c a s c ading the framers in multipair c onfiguration. alternativ ely , c an be us ed as atm one s e c ond output. configuration pins boot boot configuration pin i ? see sec t ion 5.3. reset r s t r e s e t i ? asynchronous active-low input that places the device in an inactive state. this resets the dsp and internal 8051 blocks. this pin s hould be c onnec ted to the hos t proc es s o r?s rst_out. afe interface afe_clk ? ? 19?27 mhz afe c l oc k (alway s running). connec ts direc t ly to afe pin afe_clk. 6-8 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet pin descr i ptions signal name i/o pu/ pd (1 ) description a f e _ r s t ? o ? ac tiv e -high output res e t s i gnal. connec ts direc t ly to afe pin afe_rst. a f e _ t x _ s y n c ? o ? tx serial data sync. c onnects directly to a f e pin afe_tx_sync. a f e _ r x _ s y n c ? o ? rx serial data sync. c onnects directly to a f e pin af e_rx_sync. a f e _ t x _ s e r 1 ? o ? serial tx data sample one. c onnects directly to afe pin afe_tx_ser1. afe_tx_ser2 ? o ? serial tx data s a mple two. connec ts direc t ly to afe pin afe_tx_ser2. a f e _ r x _ s e r 1 ? i ? s e rial rx data sample one. c onnects directly to afe pin af e_rx_ser1. a f e _ r x _ s e r 2 ? i ? s e rial rx data sample two. connects directly to afe pin af e_rx_ser2. a f e _ c t r l _ d a t a ? i/ o ? serial c ontrol data input/output. connec ts direc t ly to afe pin afe_ctrl_data. host port ram interface hp_adr[0?9] hos t port addres s i ? hos t port ram addres s bits 0?9. hp_dat[0?7] hos t port data i/ o (4 ) hos t port ram data bits 0?7. hp_cs host port chip selec t i (2 ) host port ra m chip-select. a c tive-low. hp_we hos t port write enable i (2 ) host port ra m write enable. a c tive-low. hp_oe host port output enable i (2 ) hos t port ram output enable. ac tiv e -low. hp_int host port external interrupt o ? a c tive-low interrupt that signifies the api protocol is complete. this output is totem-pole, and in active (high) state when reset is applied to the device. hp_clk host port clock i (2 ) hos t port data, addres s , and c ontrol s i gnal c l oc k . serial port interface p12_rxd1 debug rx data i ? debug rec e iv e data. p13_txd1 debug tx data o ? debug transmit data. p30_rxd0 rs232 rx data i ? uip interface receive data. p31_txd0 rs232 tx data o ? uip interfac e trans mit data. jtag interface trst test port reset i pu acti v e -low res e ts the tap c ontroller. if j t ag is not us ed, this pin s hould be tied high. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 6-9
pin descr i ptions m 28975 data sheet signal name i/o pu/ pd (1 ) description tdi test data in i pu j t ag tes t data input per ieee std. 1149.1-1993 . us ed for loading all s e rial ins t ruc t ions and data into internal tes t logic . sampled on the ris i ng edge of tck. tdi c an be left unc onnec ted when not being us ed bec aus e it is internally pulled high. tdo test data out o ? j t ag tes t data input per ieee std. 1149.1-1993. three-s t ate output us ed for reading all s e rial c onfiguration and tes t data from internal tes t logic . updated on the falling edge of tck. t c k t e s t cl o c k i ? j t ag tes t data input per ieee std. 1149.1-1993. used for all test interfac e and internal tes t logic operations . if unus ed, tck s hould be pulled low. tms test mode s e lect i pu j t ag tes t data input per ieee std. 1149.1-1993. input s i gnal us ed to c ontrol the tes t logic s t ate mac h ine. sampled on the ris i ng edge of tck. tms c an be left unc onnec ted when not being us ed bec aus e it is internally pulled high. miscellaneous and test modes t e s t m o d e ? i ? mus t be tied low (to gnd). t e s t _ e ? i ? mus t be tied low (to gnd). n c 1 ? i ? mus t be tied low (to gnd). t e s t _ a d 0 ? i ? mus t be tied low with an ex ternal res i s t or. t e s t _ a d 1 ? i ? mus t be tied low with an ex ternal res i s t or. t e s t _ a d 2 ? i ? mus t be tied low with an ex ternal res i s t or. n c 2 ? i ? must be tied low (to gnd). footnote: (1) internally pulled-up (pu) or pulled-down (pd) with a 50?200 k ? re si sto r . (2) when pin is not us ed, it s hould be ex ternally tied low. (3) when pin is not us ed it s hould be ex ternally tied high. (4) when pin is not us ed, it s hould be ex ternally tied by a res i s t er to high. 6.2.2 zipwireplus afe signal descriptions table 6-4 lists the zipwireplus a f e signal (pin) descriptions. t able 6-4. z i pwirep lus afe signal descriptions signal name i/o description power and ground va12 ? +12 v analog s upply a 1 2 g n d ? analog ground for +12 v analog supply va33 ? +3.3 v analog s upply a 3 3 g n d ? analog ground for +3.3 v analog supply v d 3 3 ? +3.3 v digital i/o supply 6-10 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet pin descr i ptions signal name i/o description d g n d ? digital i/o ground transmit section ldop o transmit, positive (+) line driver output ldon o trans mit, negativ e (?) line driv er output ldaop i transmit, auxiliary (+) line driver input ldaon i transmit, auxiliary (?) line driver input rcdrvp o transmit, positive (+) rc driver output rcdrvn o transmit, negative (?) rc driver output transmit references vrptx ref transmit, positive (+) voltage reference vrntx ref trans mit, negativ e (?) v o ltage referenc e transmit internal signal ld_ml ? internal line driv er s i gnal ld_mh ? internal line driv er s i gnal ld_ph ? internal line driv er s i gnal ld_pl ? internal line driv er s i gnal receive section vxp i receive, positive (+) transformer line input v x n i receive, negative (?) transformer line input v h p i receive, positive (+) hybrid analog input vhn i rec e iv e, negativ e (?) hy brid analog input receive references vrprx ref rec e iv e, pos i tiv e (+) voltage referenc e vrnrx ref receive, negative (?) v o ltage reference vbgp ref referenc e, pos i tiv e (+) band-gap referenc e vbgn ref reference, negative (?) band-gap reference vcmo ref referenc e, output common mode voltage vcmi ref referenc e, input common mode voltage avbias ref referenc e, compens ation capac itor rbias ref referenc e, current referenc e res i s t or dsp interface afe_clk i 19?27 mhz afe c l oc k (alway s running). connec ts direc t ly to dsp afe_clk. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 6-11
pin descr i ptions m 28975 data sheet signal name i/o description afe_rx_sync i rx data s t robe. connec ts direc t ly to dsp afe_rx_sync. a f e _ t x _ s y n c i txdata strobe. connects di rectly to dsp afe_tx_sync. afe_rst i/o ac tiv e -high input res e t s i gnal. connec ts direc t ly to dsp afe_rst. afe_ctrl_data i/o serial c ontrol data input/output. connec ts direc t ly to dsp afe_ctrl_data. a f e _ r x _ s e r 1 o s e rial rx data sample one (ls b ) . c onnects directly to ds p af e_rx_ser1. afe_rx_ser2 o s e rial rx data sample two (ms b ) . c onnects directly to ds p af e_rx_ser2. afe_tx_ser1 i s e rial tx data sample one (ls b ) . c onnects directly to ds p afe_tx_ser1. afe_tx_ser2 i serial tx data s a mple two (msb). connec ts direc t ly to dsp afe_tx_ser2. miscellaneous and test scan_en i asic s c an enable input, c onnec t to logic low (gnd). 6-12 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations 7.0 electrical and mechanical specifications the following specifications apply to both the zipwireplus transceiver/framer and the zipwireplus afe. 7.1 specifications for the zipwireplus transceiver/ framer and zipwireplus afe 7.1.1 recommended operating conditions table 7-1. recommended operating conditions parameter symbol min typ max units afe 12.0 v analog supply va12 11.4 12.0 12.6 v dsp 3.3 v input/output supply vio 3.15 3.3 3.45 v afe 3.3 v analog supply va33 3.15 3.30 3.45 v afe 3.3 v digital supply vd33 3 . 1 5 3.30 3.45 v dsp 1.8 v digital core vdd 1.71 1.80 1 . 8 9 v general note: a12gnd = a33gnd = gnd = dgnd = 0 v; other v o ltages with res pec t to 0 v. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-1
electrical and mechanical specif i cations m 28975 data sheet 7.1.2 recommended power sequencing pow e r up sequencing involves the order of pow ering up the io and core supplies and the period of tim e betw een pow ering up these supplies. the recom m e nded sequence for the m28975 is as follow s : 5 . 0 v (vgnn) 3 . 3 v (vddo, vd3 3 an d va3 3 ) 1 . 8 v (vdd) there is no m i nim u m or m a xim u m tim e betw een supplies. the sequencing of the 12.0 v (v a 12) is not critical. the m28975 contains power sequencing protection, which will place the output drivers in a high im pedances state when the io supply (3.3 v) is detected and place the output drivers in a low im pedance state w h en the core supply (1.8 v ) is detected. without this pow er sequencing protection, w h en the io supply (3.3 v ) is pow ered up first, the output drivers can be in an inde term inate state until the core supply (1.8 v) is pow ered up. if this indeterm inate state lasts long enough (several m s ), the unknow n state of the output drivers can cause sy stem problem s. this pow er sequencing protection does not rem ove the requirem e nt for the above power sequence. if the above power seque nce is not followed, there will be potentially a large forward bias current draw n until the io supply (3.3 v) is powered up. this can cause a reliability issue. 7.1.3 absolute maximum ratings table 7-2. absolute maximum ratings parameter symbol min typ max units v a 1 2 v a 1 2 ? 1 2 . 0 ? v v i o v i o ? 0 . 3 3.3 4.6 v v a 3 3 v a 3 3 ? 0 . 3 3 . 3 0 3.45 ? vd33 vd33 ? 0 . 3 3 . 3 0 3.45 ? vdd vdd ?0.3 1.8 2.5 v v voltage on any signal pin ? gnd?0.3 ? vio + 0.3 v input current, any pin ex c ept s upplies imax ? ? 10 ma analog input voltage ? ?0.3 ? vaa + 0.3 v digital input voltage for trans c e iv er and framer ? ?0.3 ? v gnn +0.3 v digital input voltage for afe ? ?0.3 ? 3.45 v ambient operating temperature t a ?40 25 +85 o c j unc tion temperature t j ? ? 1 2 5 o c storage temperature (ambient) t sa ?65 ? 1 5 0 o c 7-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations parameter symbol min typ max units soldering temperature tsol ?65 ? 260 o c vapor phas e soldering tvsol ?65 ? 2 2 0 o c air flow 0 ? 0 ? l . f . p . m . general note: operation bey ond thes e limits may c aus e permanent damage to the dev ic e. normal operation is not guaranteed at thes e ex treme c onditions . 7.2 thermal characteristics 7.2.1 zipwireplus afe for the 48-pin etq fp (a fe) w ith 0 m / s of airflow , ja ~ 27 c/w. 7.2.2 zipwireplus transceiver/framer for the 13 13 m m fpbga (transceiver/fram e r) with 0 m / s of airflow, ja ~ 44 c/w. for the 176-pin lq fp (transceiver/fram e r) w ith 0 m / s of airflow , ja ~ 32 c/w. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-3
electrical and mechanical specif i cations m 28975 data sheet 7.3 specifications for zipwireplus transceiver/framer only 7.3.1 power dissipation table 7-3 show s the breakdow n for the zipwireplus transceiver/fram e r pow er dissipation. table 7-3. zipwireplus trans ceiver/framer p o wer dissipation parameter symbol min typ max units dsp/framer, +1.8 v 192 k bps 1,168 k bps 1,552 k bps 2,320 k bps pd dsp 1.8 ? 130 190 220 290 ? m w dsp, +3.3 v 192 k bps 1,168 k bps 1,552 k bps 2,320 k bps pd dsp 3.3 ? 18 18 20 25 ? m w 7.3.2 dc characteristics table 7-4 lists the transcei ver?s dc characteristics. table 7-4. transceiver/framer dc characteristics parameter symbol min typ max units digital inputs input high voltage vih 2.0 ? v gnn +0.25 v input low voltage vil 0 ? 0.8 v input leak age current iil/iih -40 ? 40 n a input capac itanc e cin ? ? ? pf digital outputs output high voltage voh 2.4 ? 3.3 v output low voltage vol ? ? 0.4 v three-state output leak age ilk -40 ? 40 n a output capac itanc e c out ? ? ? p f digital bi-directionals three-state output leak age ilk ? ? ? na input/output capac itanc e cinout ? ? ? pf 7-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations 7.3.3 host port ram interface timing figure 7-1 and figure 7-2 illustrate the hos t port ram interface tim ing. table 7-5 lists the host port ram interface tim ing. figure 7- 1. host p o rt write cycle t iming 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-5
electrical and mechanical specif i cations m 28975 data sheet figure 7-2. host port read cycle timing table 7-5. host port timing symbol parameter minimum max i mum units t cp hos t port c l oc k period 18 ? ns t sc chip s e lec t s e tup to hp_c lk 1 ? ns t hc chip s e lec t hold after hp_c lk 2 ? ns t sw write enable s e tup to hp_c lk 1 ? ns t hw write enable hold after hp_c lk 2 ? ns t sd data s e tup to hp_c lk 2 ? ns t hd data hold after hp_c lk 2 ? ns t sa addres s s e tup to hp_c lk 1 ? ns t ha addres s hold after hp_c lk 2 ? ns t ra read ac c e s s time ? 8 ns t zo output enable to data driv en ? 5 ns t oz output enable to data three-s t ate 6 ? ns 7-6 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations 7.3.4 dsl framer timing requirements figure 7-3. input clock requirements table 7-6: input clock timing symbol parameter minimum maximum units ? tpclk, pextclk, tnbclk ? ? ? 1/t p f r e q u e n c y 0 . 0 6 4 1 8 . 4 3 2 mhz t h cloc k width high 21.7 ? ns t 1 cloc k width low 21.7 ? ns t r cl o ck ri se ti m e ? 2 0 ns t f clock fall time ? 20 ns figure 7-4. input setup and hold requirements table 7-7: input setup and hold timing symbol parameter minimum max i mum units ? tpdat, tpinsdat, tpmfsync, tnbdat, tnbsync, sif_tx_data, sif_tx_soc ? ? ? t s input setup time 35 ? ns t hl d input hold time 10 ? ns 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-7
electrical and mechanical specif i cations m 28975 data sheet 7.3.5 dsl framer switching characteristics figure 7-5. output characteristics table 7-8: output timing symbol parameter minimum maximum units ? rpclk, rpdpllclk, rnbclk, sif_tx_clk, sif_rx_clk ? ? ? 1/t p f r e q u e n c y 0 . 0 6 4 1 6 . 3 8 4 mhz t h cloc k width high tp/2 ? 20 tp/2 + 20 ns t 1 cloc k width low tp/2 ? 20 tp/2 + 20 ns t r cl o ck ri se ti m e ? 1 5 ns t f clock fall time ? 15 ns ? rpdat, rpdrop, rpmfsync, tpmfsync, sif_rx_data, sif_rx_soc ? ? ? t hl d output data hold 0 ? ns t dl y output data delay ? 25 ns 7-8 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations 7.3.6 utopia interface timing figure 7-6 through figure 7-7 and table 7-9 through table 7-10 show the tim ing requirem e nts and characteristics of the utopia interface. figure 7-6. utopia transmit timing diagram 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-9
electrical and mechanical specif i cations m 28975 data sheet table 7-9. utopia transmit timing table label parameter minimum maximum units t pw l puls e width low, atm_tx_clk 8 ? ns t pw h puls e width high, atm_tx_clk 8 ? ns t pe r p e r i o d , a t m _ t x _ c l k 20 ? ns t s1 setup, atm_tx_enb# to the ri sing edge of atm_tx_clk 4 ? ns t h1 hold, atm_tx_enb# from the rising edge of atm_tx_clk 1 ? ns t s2 setup, atm_tx_addr to the rising edge of atm_tx_clk 4 ? ns t h2 hold, atm_tx_addr from the rising edge of atm_tx_clk 1 ? ns t s3 setup, atm_tx_data to the rising edge of atm_tx_clk 4 ? ns t h3 hold, atm_tx_data from the rising edge of atm_tx_clk 1 ? ns t s4 setup, atm_tx_prty to the rising edge of atm_tx_clk 4 ? ns t h4 hold, atm_tx_prty from the rising edge of atm_tx_clk 1 ? ns t s5 setup, atm_tx_soc to the rising edge of atm_tx_clk 4 ? ns t h5 hold, atm_tx_soc from the rising edge of atm_tx_clk 1 ? ns t en enable, atm_tx_clav from the rising edge of atm_tx_clk 1 4 ns t pd propagation delay, atm_tx_cl av from the rising edge of atm_tx_clk 1 9 ns t di s disable, atm_tx_clav from the rising edge of atm_tx_clk 1 4 ns 7-10 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations figure 7-7. utopia receive timing diagram 500015_104 atm_rx_enb# atm_rx_addr atm_rx_clk atm_rx_data atm_rx_prty atm_rx_soc atm_rx_clav t s1 t h1 t s2 t pwl t pwh t en1 t pd1 t dis1 t en2 t pd2 t dis2 t en3 t pd3 t dis3 t en4 t pd4 t dis4 t per t h2 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-11
electrical and mechanical specif i cations m 28975 data sheet table 7-10. utopia receive timing table label parameter minimum maximum units t pw l puls e width low, atm_rx_clk 8 ? ns t pw h puls e width high, atm_rx_clk 8 ? ns t per p e r i o d , a t m _ r x _ c l k 2 0 ? ns t s1 setup, atm_rx_enb# to the rising edge of atm_rx_clk 4 ? ns t h1 hold, atm_rx_enb# from the ris i ng edge of atm_rx_clk 1 ? ns t s2 setup, atm_rx_addr to the rising edge of atm_rx_clk 4 ? ns t h2 hold, atm_rx_addr from the rising edge of atm_rx_clk 1 ? ns t en1 enable, atm_rx_data[15:0] from the ris i ng edge of atm_rx_clk 2 1 0 ns t pd1 propagation delay , atm_rx_data[15:0] from the ris i ng edge of atm_rx_clk 1 14 ns t di s1 dis able, atm_rx_data[15:0] from the ris i ng edge of atm_rx_clk 2 10 ns t en2 enable, atm_rx_prty from the ris i ng edge of atm_rx_clk 2 10 ns t pd2 propagation delay , atm_rx_prty from the ris i ng edge of atm_rx_clk 1 1 4 ns t di s2 dis able, atm_rx_prty from the ris i ng edge of atm_rx_clk 2 10 ns t en3 enable, atm_rx_soc from the ris i ng edge of atm_rx_clk 2 10 ns t pd3 propagation delay , atm_rx_soc from the ris i ng edge of atm_rx_clk 1 1 4 ns t di s3 dis able, atm_rx_soc from the ris i ng edge of atm_rx_clk 2 10 ns t en4 enable, atm_rx_clav from the ris i ng edge of atm_rx_clk 1 8 ns t pd4 propagation delay , atm_rx_clav from the ris i ng edge of atm_rx_clk 1 8 ns t di s4 dis able, atm_rx_clav from the ris i ng edge of atm_rx_clk 1 8 ns 7-12 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations 7.4 specifications for zipwireplus afe only the follow i ng specifications apply only to the zipwireplus a f e. 7.4.1 power consumption table 7-11 show s the breakdow n for the single channel zipwireplus a f e pow er consum ption for 1,552 kbps g . shdsl enhanced perform ance a s y m m e tric psd (epa p) and 2,320 kbps g . shdsl sy m m e tric psd m ode. pow e r consum ption for other data rates will be sim ilar. these pow er values assum e norm a l operating m odes of random (scram bled) data with a 10 kft. 26 awg line the m a xim u m values are for worst case te m p erature, voltage, and silicon process. the pow er consum ption includes the pow er delivered to the d s l line. in epa p m ode, the pow er delivered to the load is ~100 m w . in sy m m e tric psd m ode, the power delivered to the load is ~50 m w . figure 7-8. z i pwirep lus afe p o wer dissipation parameter condition symbol min typ max units afe, +12.0 v epap pd afe 12.0 ? 4 2 0 ? mw s y m p s d ? 3 5 0 ? mw afe, +3.3 v ? pd af e 3.30 ? 410 ? mw 7.4.2 dc characteristics t able 7-11. afe dc characteristics. parameter symbol min typ max units digital inputs input high voltage vih 2.50 ? 3.45 v input low voltage vil gnd ? 0.4 v v input leak age current iil/iih ?10 ? 1 0 a input capac itanc e cin ? 2 . 9 ? pf digital outputs output high voltage voh 0.9 vio ? vio v output low voltage vol gnd ? 0 . 1 v i o v three-state output leak age i l k 1 0 ? 1 0 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-13
electrical and mechanical specif i cations m 28975 data sheet parameter symbol min typ max units output capac itanc e cin ? 3.1 ? pf digital bidirectionals three-state output leak age i l k ? 1 0 ? 1 0 a input/output capac itanc e cinout ? 3.0 ? pf 7-14 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations 7.5 mechanical specifications 7.5.1 the 13 x 13 mm fpbga figure 7-9 illustrates the 13 13 fpbga for the dsp/fram er. figure 7-9. package outline for 13 x 13 fpbga 101083_081 dim. millimeters ref: 176-pin fpbga (gp00-d528-001)** inches min. max. min. max. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r d1 d d a1 a a1 a2 d d1 m n e b c coplanarity warpage 0.31 0.65 0.29 0.012 0.026 0.011 0.016 0.030 0.015 0.41 0.75 0.39 1.41 max 13.00 ref 11.20 ref 0.80 ref 0.46 ref 0.10 max 0.10 max 0.056 max 0.512 ref 0.441 ref 0.031 ref 0.018 ref 0.004 max 0.004 max 15 176 a2 a c d1 e e b top view bottom view 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-15
electrical and mechanical specif i cations m 28975 data sheet 7.5.2 176-pin lqfp figure 7-10 illustrates the 176-pin lqfp for the dsp/fram er. figure 7-10. mechanical drawing 176-pin lqfp 7-16 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet electrical and mechanical specif i cations 7.5.3 48-pin etqfp figure 7-11 illustrates the 48-pin etqfp for the afe/line driver figure 7-11. top and bottom view of a 7x7mm 48-pin etqfp 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential 7-17
electrical and mechanical specif i cations m 28975 data sheet this page intentionally left blank. 7-18 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix a: power consum ption appendix a: power consumption table a- 1: power consumption of the m28975 in idle mode/reset stage current (ma) dsp afe total power mode 1.8vdd 3.3vddo 3.3v 12vaa power/port power/port per port dsp core dsp i/o afe afe (w) (w) (w) i d l e 8 6 . 0 0 5 . 2 0 1 1 8 . 5 0 2 2 . 5 8 0 . 1 7 2 0 . 6 6 2 0 . 8 3 4 hold res e t 80.00 4.89 87.30 0.17 0.160 0.290 0.450 table a- 2: power consumption of the m 28975 in hdsl2 mode at 9 kft (26 awg) loop dsl current (ma) dsp afe total power line rate 1.8vdd 3.3vddo 3.3v 12vaa power/port power/port per port (kbps) dsp core dsp i/o afe afe (w) (w) (w) 1 5 5 2 1 2 5 . 0 0 5 . 4 5 1 1 5 . 2 0 3 3 . 8 5 0 . 2 4 3 0 . 7 8 6 1 . 0 2 9 table a- 3: power consumption of m28975 in g.hs dsl mode at 9 kft (26 awg) loop in annex a symmetric mode 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential a-1 dsl current (ma) dsp afe total power line rate 1.8vdd 3.3vddo 3.3v 12vaa power/port power/port per port (kbps) dsp core dsp i/o afe afe (w) (w) (w) 1 4 4 n / a n / a n / a n / a n / a n / a n / a 2 0 0 6 5 . 0 0 4 . 9 5 1 1 3 . 0 0 3 0 . 0 1 0 . 1 3 3 0 . 7 3 3 0 . 8 6 6 2 0 8 6 5 . 0 0 4 . 9 5 1 1 3 . 1 0 2 9 . 8 5 0 . 1 3 3 0 . 7 3 1 0 . 8 6 5 2 7 2 6 8 . 0 0 4 . 9 7 1 1 3 . 2 0 2 9 . 0 1 0 . 1 3 9 0 . 7 2 2 0 . 8 6 0 3 9 2 7 3 . 0 0 5 . 0 1 1 1 3 . 2 0 2 8 . 4 4 0 . 1 4 8 0 . 7 1 5 0 . 8 6 3 4 0 0 7 3 . 0 0 5 . 0 1 1 1 3 . 1 0 2 8 . 4 0 0 . 1 4 8 0 . 7 1 4 0 . 8 6 2 5 2 8 7 9 . 0 0 5 . 0 5 1 1 3 . 3 0 2 8 . 1 7 0 . 1 5 9 0 . 7 1 2 0 . 8 7 1 7 7 6 9 0 . 0 0 5 . 1 3 1 1 3 . 4 0 2 8 . 1 6 0 . 1 7 9 0 . 7 1 2 0 . 8 9 1 7 8 4 9 1 . 0 0 5 . 1 5 1 1 3 . 7 0 2 8 . 2 1 0 . 1 8 1 0 . 7 1 4 0 . 8 9 5 1 0 4 0 1 0 1 . 0 0 5 . 2 4 1 1 4 . 4 0 2 8 . 2 8 0 . 1 9 9 0 . 7 1 7 0 . 9 1 6 1 1 6 8 1 0 5 . 0 0 5 . 2 7 1 1 4 . 1 0 2 8 . 3 2 0 . 2 0 6 0 . 7 1 6 0 . 9 2 3 1 5 5 2 1 2 4 . 0 0 5 . 4 5 1 1 5 . 5 0 2 8 . 4 4 0 . 2 4 1 0 . 7 2 2 0 . 9 6 4
appendix a: power consum ption m 28975 data sheet dsl current (ma) dsp afe total power line rate 1.8vdd 3.3vddo 3.3v 12vaa power/port power/port per port (kbps) dsp core dsp i/o afe afe (w) (w) (w) 2 0 5 6 1 4 4 . 0 0 5 . 5 8 1 1 5 . 3 0 2 8 . 6 2 0 . 2 7 8 0 . 7 2 4 1 . 0 0 2 2 0 6 4 1 4 5 . 0 0 5 . 6 0 1 1 5 . 4 0 2 8 . 6 2 0 . 2 7 9 0 . 7 2 4 1 . 0 0 4 2 3 1 2 1 6 1 . 0 0 5 . 8 0 1 1 8 . 5 0 2 8 . 6 2 0 . 3 0 9 0 . 7 3 4 1 . 0 4 3 2 3 2 0 1 6 2 . 0 0 5 . 8 1 1 1 8 . 6 0 2 8 . 6 2 0 . 3 1 1 0 . 7 3 5 1 . 0 4 6 t able a- 4: co, annex a, asymmetric, 9 kft 26 awg dsl current (ma) dsp afe total power line rate 1.8vdd 3.3vddo 3.3v 12vaa power/port power/port per port (kbps) dsp core dsp i/o afe afe (w) (w) (w) 1 5 5 2 1 2 3 . 0 0 5 . 4 5 1 1 5 . 5 0 3 8 . 2 0 0 . 2 3 9 0 . 8 4 0 1 . 0 7 9 table a- 5: co, annex b, asymmetric, 9kft 26 awg dsl current (ma) dsp afe total power line rate 1.8vdd 3.3vddo 3.3v 12vaa power/port power/port per port (kbps) dsp core dsp i/o afe afe (w) (w) (w) 2 0 5 6 1 4 2 . 0 0 5 . 5 8 1 1 6 . 5 0 3 5 . 2 6 0 . 2 7 4 0 . 8 0 8 1 . 0 8 2 2 3 1 2 1 5 8 . 0 0 5 . 8 0 1 2 0 . 0 0 3 2 . 0 0 0 . 3 0 4 0 . 7 8 0 1 . 0 8 4 a-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m28975 data sheet appendix b: surface m ount application note?fpbga package appendix b: surface mount application note?fpbga package family b.1 purpose the fine pitch ball grid array (fpbga) p ackage features a lam i nate bga substrate w ith solder balls on a 1.0 m m or finer ball p itch. to m a ke optim um use of this near chip scale package, the pwb m u st be designed w ith this technology in m i nd. this application note will focus on the specifics of integrating the fpbga into the pwb design. b.2 solder pad geometry for portable product applications where m ech anical shock m a y occur, it is critical that the adhesion between the solder joint pads and the core m a terial of the pwb does not fail. in order to overcom e this failure m ode, it is recom m e nded that solder m a sk defined (smd ) pads be used. table b- 1 show s the recom m e nded solder joint pad diam eter and solder m a sk opening diam eter. figure b- 1 show s a typical solder joint pad with dog bone trace to via. if m i cro via (150 m or less) technology is available, the m i crovia can be placed directly in the solder joint pad. the recom m e nded pad geom etry is given in figure b- 2. table b- 1: recommended pad geometry solder ball pitch solder ball diameter solder pad diameter (d1) solder mask opening (d2) 1.0 mm 0.50 mm 0.53 mm 0.38 mm 0.8 mm 0.46 mm 0.45 mm 0.30 mm 0.5 mm 0.35 mm 0.35 mm 0.20 mm 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential b-1
appendix b: surface mount application note?fpbga package m28975 data sheet figure b- 1: recommended smd pad geometry using standard via technology figure b- 2: recommended smd pad geometry using micro via technology b-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m28975 data sheet appendix b: surface m ount application note?fpbga package b.3 solder stencil determination solder and solder paste volum e control is critical for smt assem b ly of fpbga packages onto the pwb. stencil thickness and aperture openings should be optim ized according to the optim al solder volum e. in general, fpbga packages can be reflow ed on boards using a range of stencil thickness from 4 to 6 m ils. stencil thickness sm aller than 4 m ils should be avoided to prevent insufficient solder joint volum e. to m i nim i ze the risk of shorting adj acent solder balls, it is suggested that the aperture opening for the solder pads be reduced to 2 m ils sm aller in diam eter than the solder m a sk opening. see figure b- 1 for detail. in general, the thicker the stencil, the sm aller the aperture should be. figure b- 3: recommended stencil aper ture opening for the fp bga solder p ad b.4 solder reflow profile standard no-clean solder paste is generally recom m e nded. if another ty pe of flux is used, com p lete rem oval of flux residual m a y be necessary . standard smt reflow profiles can be used to surface m ount the fpbga packages to the pwb. a range of recom m e nded param e ters for the smt reflow profile is listed in table b- 2. a dditional soak tim e and slow er preheating tim e m a y be required to im prove the outgassing of solder paste during smt reflow . table b- 2: recommended smt reflow profile preheat slope (ambient to 120 c) 1? 2 c/s e c tes t pac k age 12x 12-160 pin, 0.8 pitc h soak slope (120 to 183 c) 0.3? 0.6 c/s e c pwb fr4 time abov e reflow (> 183 c) 50? 80 s e c solder pas t e no-c lean sn63pb37 peak temperature 220 +/? 5 c ? ? cooling rate < 6 c/s e c ? ? s t encil s s laser-cut, 5-mil thickness, trapezoidal ? ? 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential b-3
appendix b: surface mount application note?fpbga package m28975 data sheet figure b- 4: typical temperature profile for surface mount of fpbga b-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m28975 data sheet appendix c: surface m ount application note? elqfp package appendix c: surface mount application note? elqfp package family c.1 purpose the elq fp package features an exposed die paddle to im prove both therm a l and electrical perform ance. to m a ke optim um use of these perform ance im provem e nts, the pwb m u st be designed w ith this technology in m i nd. this application note focuses on the specifics of integrating the elqfp with the pwb design. c.2 center pad geometry to take advantage of elq fp perform ance im provem e nts, a solder-tinned-copper pad w ith therm a l vias is required on the pwb. the pad size should be at least 0.25 m m larger on all sides than the dim e nsioned exposed pad on the device technical specification sheet w ith the solder m a sk opening equal to the dim e nsioned exposed pad on the sheet. the result is a solder m a sk defined pad. an array of 0.33 m m diam eter therm a l vias plated with 1 oz. copper should be placed w ithin the exposed region of the pad and shorted to the ground plane of the pwb. this therm a l via pattern represents a copper cross section in the barrel of the therm a l via of approxim a tely 1% of the total center pad area. if the plating thickness is not sufficient to effectively plug the barrel of the via when plated, then solder m a sk should be used to cap the vias w ith a dim e nsion equal to the via diam eter +0.1 m m m i nim u m . this will prevent the solder from being wicked through the therm a l via and potentially creating a solder void in the region betw een the package bottom and the center pad on the surface of the pw b. figure c- 1 shows the copper pad footprint, therm a l vias and the solder m a sk opening defining the center pad. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential c-1
appendix c: surface mount application note? elqfp package m28975 data sheet figure c- 1: top metalization and solder ma sk definition for the 48ld elqfp, where a = b = 7.40 mm, c = 0.50 mm, d = 0.25 mm, e = 1.00 mm, and f = 4.70 mm c.3 solder stencil determination a general guideline w ould be to use the thicke st solder stencil that works well for the products being assem b led for the m o st process m a rgin in assem b ling therm a lly enhanced packages to a pwb. a standoff height of 2.0 to 4.2 m ils provides good solder joints for both the leads and the center pad. this is achieved using a stencil thickness of 5, 6, or 7 m ils. c.4 solder reflow profile the elqfp reflow profile for board assem b ly does not have to be m odified from the standard lqfp reflow profile because the construction of the package does not add therm a l m a ss. additional, the only new therm a l load is due to the increased solder area betw een the exposed die pad on the package and the center pad on the pwb. a range of recom m e nded param e ters for the smt reflow profile is listed in table c- 1. a dditional soak tim e and slow er preheating tim e m a y be required to im prove the outgassing of solder paste during smt reflow . figure c- 2 show s a ty pical reflow profile for the 48 pin elq fp. table c- 1: recommended smt reflow profile preheat slope (ambient to 120 c) 1?2 c/s e c tes t pac k age 48 pin elqfp soak slope (120 to 183 c) 0.3?0.6 c/s e c pwb fr4 time abov e reflow (>183 c) 50?80 s e c s o lder p aste no-clean ? s n 6 3 p b 3 7 ? ? peak temperature 220 +/?5 c ? ? cooling rate < 6 c/s e c ? ? stenc il ss las e r-c ut, 5-mil thic k nes s ? ? ? c-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m28975 data sheet appendix c: surface m ount application note? elqfp package figure c- 2: typical temperature profile for surface mount of elqfp 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential c-3
appendix c: surface mount application note? elqfp package m28975 data sheet this page intentionally left blank. c-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix d: e xposed pad t h in quad flat pack ( e t q fp) appendix d: exposed pad thin quad flat pack (etqfp) abstract the exposed thin q u ad flat pack ( etq fp) package provides greater design flexibility and increased therm a l efficiency , while using a standard size ic package. exposed pad im proved perform ance perm its higher clock speeds, m o re com p act sy stem s, and m o re aggressive design criteria. etq fp therm a l perform ance is better than in standard packages. h o w e ver, in order to m a ke optim um use of the therm a l efficiencies designed into the etqfp, the pcb m u st be designed with this package in m i nd. the follow i ng sections of this docum ent provide m o re inform ation regarding the therm a l perform ance and pwb design for mindspeed etq fps. d.1 introduction the etq fp is im plem ented using a standard epoxy -resin package m o ld com pound. the integrated circuit die is attached to the lead-fram e die pad using a therm a lly conductive epoxy . the lead fram e is designed w ith a deep dow nset of the die attach pad so that it is exposed on the bottom surface of the package after m o ld. this provides an extrem ely low therm a l resistance between the ic junction and the exterior of the surface. the external surface of the die pad can be attached to the pcb using standard solder reflow techniques. this allows efficient attachm e nt to the board, and perm its the board structure to be used as a heat sink for the ic. using therm a l vias, the lead fram e die pad can be attached to a ground plane or special heat sink structure designed into the pcb. figure d - 1 show s the schem a tic of the package com ponents. 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential d-1
appendix d: e xposed pad t h in quad flat pack ( e t q fp) m 28975 data sheet figure d- 1: schematic representation of the package components d.2 package thermal characterization d.2.1 heat removal path the internal heat rem oval path is designed to transfer heat from the top surface of the die to the die pad and then directly to the printed circuit board (pcb) through a center solder pad. the pcb m u st be designed to rem ove heat from the package efficiently . a t a m i nim u m , there m u st be an area of solder-tinned-copper underneath the etqfp, called a therm a l land. heat is transferred from the therm a l land to the environm ent through therm a l vias de signed w ithin the pcb structure. d.2.2 thermal lands a therm a l land is required on the surface of the pcb directly underneath the body of the exposed package. during norm a l surface m ount re-flow, the exposed pad on the underside of the package is soldered to this therm a l land to create an efficient therm a l path. the size of therm a l path is as large as needed to dissipate the required heat. for sim p le double-sided pcbs having no internal lay e rs, the surface lay e rs m u st be used to rem ove heat. figure d - 2 show s a sam p le package detail, including required solder m a sk and therm a l land pattern for an eq tfp. the designer m a y consider external m eans of heat conduction, such as attaching the copper planes to a convenient chassis m e m b er or other hardw a re convection. d-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix d: e xposed pad t h in quad flat pack ( e t q fp) figure d- 2: package and pcb land configuration 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential d-3
appendix d: e xposed pad t h in quad flat pack ( e t q fp) m 28975 data sheet an array of 0.33 m m diam eter therm a l vias plated with 1 oz. copper m u st be placed on the pad and shorted to the ground plane of the pcb. if the plating thickness in the exposed region of the center pad is not sufficient to effectively plug the barrel of the via w h en plated, then solder m a sk should be used to cap the vias; the m a sk diam eter should have a dim e nsion equal to the via diam eter + 0.1 m m m i nim u m . this will prevent the solder from w i cking through the therm a l via, potentially creating a solder void in the region between the package bottom and the center pad on the surface of the pcb. table d - 1 show s the dim e nsi ons for the entire etqfp package fam ily. table d- 1: dimensional parameters (mm) packag e ty pe a b c d e f re c o mme nde d a rray of the rma l via s 48 pin etqfp 7.40 7.40 0.50 0.25 1.00 25 s q . 5 x 5 64 pin etqfp 10.40 10.40 0.50 0.25 1 . 0 56.25 8 x 8 80 pin etqfp 14.40 14.40 0.50 0.25 1.0 106.09 10 x 10 d-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix d: e xposed pad t h in quad flat pack ( e t q fp) d.3 pcb design therm a l vias are the prim ary m e thod of h eat transfer from the pcb therm a l land to the internal copper planes or to other heat rem oval sinks. the num ber of vias, the size of the vias used, and the construction of the vias is im portant in obtaining the best package therm a l perform ance and the package/pcb assem b ly. therm a l perform ance analysis shows that there is a point of dim i nishing returns w h ere additional vias will not im prove heat tran sfer through the board, which is a function of die size and the num ber of therm a l via. the pcb internal structure plays a very im portant role in package therm a l perform ance. figure d - 3 and figure d - 4 show the pcb structure for a 2- and a 6-lay e r design, respectively . pcb designs w ith m o re than tw o lay e rs should have all therm a l vias connected to the ground plane. figure d- 3: internal structure for a two layer pcb. figure d- 4: internal structure f o r a six l a yer p cb 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential d-5
appendix d: e xposed pad t h in quad flat pack ( e t q fp) m 28975 data sheet d.4 thermal test structure d.4.1 test environment package therm a l perform ance has been te sted following jedec standards. the etq fp package is m ounted at the center of a 100 m m x 100 m m six lay e r test board and is tested under different air flow velocities. figure d- 5 shows the sy stem configuration. figure d- 5: test performance structure (a = 100 mm, b = 100 mm, lp = 1.40 mm, lb = 1.60 mm) d.4.2 thermal test boards tw o different test boards have been used to evaluate package therm a l perform ance for both w o rst and best conditions. table d - 1 show s the specifications of these test boards. table d- 2: specification for a two-layer test board drawing number tr03-t1 subs trate material fr-4 thic k nes s 1.6 mm stac k up (# s i gnal lay e rs , # cu planes ) 1s0p cu cov e rage (s ignal lay e r - top/bottom) 10% cu cov e rage (power/gnd lay e r) 100% inner cu thic k nes s (s pec ) 35 3.5 table d- 3: specification for a four-layer test board drawing number tr03-t1 subs trate material fr-4 th i ckn e ss 1.6 mm stac k up (# s i gnal lay e rs , # cu planes ) 1s2p d-6 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix d: e xposed pad t h in quad flat pack ( e t q fp) drawing number tr03-t1 cu cov e rage (s ignal lay e r - top/bottom) 10% cu cov e rage (power/gnd lay e r) 100% inner cu thic k nes s (s pec ) 35 3.5 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential d-7
appendix d: e xposed pad t h in quad flat pack ( e t q fp) m 28975 data sheet d.5 package thermal performance d.5.1 calculation guidelines maxim u m junction tem p erature can be calculated as: t j = p ja + t a (1) where: ja = equivalent package therm a l resistance (c/w) t j = maxim u m junction tem p erature (c) t a = am bient tem p erature (c) p = package total power dissipation value (w) d.5.2 package thermal resistance delco therm a l test chips are used to estim ate package therm a l perform ance. table d - 4 show s therm a l die specifications table d- 4: specification for delco thermal test chips manufacturer delco delco delco dimens ions 3.81 mm x 3.81 mm 6.35 mm x 6.35 mm 7.8 mm x 7.8 mm thic k nes s 0.33 mm 0.45 mm 0.5 mm figure d- 6 shows package therm a l resistance as a function of airflow velocity for a 48 etq fp package using tw o different test boards, specified in table d - 1 and table d - 3 and a prediction for a 6-lay e r pcb design. figure d - 7 and figure d - 8 show the sim ilar inform ation for a 64 and 80 etq fp package. table d - 5 show s the test condition for each package type. table d- 5: test conditions package type 48 eqtfp 64 etqfp 80 etqfp body siz e 7 mm x 7 mm 10 mm x 10 mm 14 mm x 14 mm die size 3.81 mm x 3.81 mm 6.35 mm x 6.35 mm 7.8 mm x 7.8 mm die pad siz e 5 mm x 5 mm 7.50 mm x 7.50 mm 9.50 mm x 9.50 mm d-8 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix d: e xposed pad t h in quad flat pack ( e t q fp) figure d- 6: package thermal resistance as a function of airflow velocity for a 48 et qfp figure d- 7: package thermal resistance as a function of airflow velocity for a 64 et qfp figure d- 8 illustrates the package therm a l resistance as a function of airflow velocity for a 80 etq fp. package. table d - 1 show s the test conditions. figure d- 8: package thermal resistance as a function of airflow velocity for a 80 et qfp 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential d-9
appendix d: e xposed pad t h in quad flat pack ( e t q fp) m 28975 data sheet d.6 solder stencil determination the thickest possible solder m a sk, consistent w ith the com ponents being assem b led to the pwb and the with the pwb surface m ount process, should be used. a standoff height of 2.0 to 4.2 m ils provides good solder joints for both the leads and the center pad. this is achieved using a stencil thickness of 5, 6, or 7 m ils. d.7 solder reflow profile the etqfp uses the standard tqfp re-fl ow profile because the etqfp package construction does not add therm a l m a ss. there is m i nim a l additional therm a l load due to the increased solder area betw een the exposed die pad on the package and the center pad on the pcb. figure d - 9 and figure d - 10 show ty pical ir reflow profiles for sn63:pb37 solder in the cases of natu ral convection and forced convection ovens. figure d- 9 illustrates the ty pical ir refl ow profile for eutectic sn63:pb37. peak tem p erature should be approxim a tely 220 o c, and the exposure tim e should norm a lly be less than 1.0 m i nute at tem p eratures above 183 o c. figure d- 9: ir reflow profile d-10 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix d: e xposed pad t h in quad flat pack ( e t q fp) figure d- 10 illustrates the ty pical forced convection reflow profile for eutectic sn63:pb37. peak tem p erature should be approxim a tely 235 o c, and the exposure tim e should norm a lly be less than 1.2 m i nutes at tem p erature above 183 o c. belt speed = 30 inches/m inute (top and bottom setting), fan speed = 2500 rpm, and nitrogen level = 1200 scfh . figure d- 10: forced convection reflow profile note: zone 1 = 185 c zone 2 = 185 c zone 3 = 175 c zone 4 = 175 c zone 5 = 18 0 c zone 6 = 190 c zone 7 = 230 c zone 8 = 270 c 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential d-11
appendix d: e xposed pad t h in quad flat pack ( e t q fp) m 28975 data sheet this page intentionally left blank. d-12 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix e : acr ony m s and abbr eviations appendix e: acronyms and abbreviations adc (a/d) analog-to-digital converter a f e a n alog front end ais alarm indication signal ansi american national standards institute api application programming interface atm-tc asynchronous transfer mode-transmission convergence ber bit error rate bga ball grid array bp bit pump bpv bipolar violation bt bit pump transceiver ca s channel a ssociated signaling channel unit hdsl fram er (nam e com e s from hdsl1 fram er) crc-n cyclic redundancy check-n cu channel unit or hdsl framer dac (d/a) digital-to-analog converter dfe decision feedback equalizer dip dual in-line package do wn stream fro m th e htu-c to ward s th e htu-r (in c lu d e s regenerators) dpll digital phase lock loop dsd dsl sync detector dsl digital subscriber line dsl fram er zipwireplus dsl fram er block dsp digital signal processor ec echo canceller eoc embedded operations channel 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential e-1
appendix e : acr ony m s and a bbr eviations m 28975 data sheet etq fp exposed pad tw in q u ad flat pack etsi european telecom m unications standards institute ev m e v a l u a t i o n m o d u l e febe far end block error (the far end reported a crc error) fext far end cross talk ffe feed forward equalizer fifo first-in first-out fpbga fine pitch ball grid array fr framer h2 tu hdsl2 term in al un it h d l c h i gh-level d a ta link controller hdsl high-bit-rate digital subscriber line hec head error control htu hdsl term in al un it htu-c o r cot o r ltu central office terminal or local terminal unit htu-r o r rt o r ntu rem o te term inal or network term inal unit led light em itting diode itu international telecom m unications u n ion lo s loss of signal lqfp low profile quad flat pack mpu micro processor unit near en d cro ss talk nni network node interface np0 negative positive zero oof ou t o f fram e p2mp point to multipoint pam pulse amplitude modulation pcm pulse code modulation pll phase lock loop ppm parts per million pra primary rate access prbs pseudo-random bit sequence psd power spectral density ram random access memory next e-2 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d
m 28975 data sheet appendix e : acr ony m s and abbr eviations rom read only memory sbid stuff bit id ses severe error second sif serial interface stp serial test port tc transmission convergence tcm time code modulation tqfp thin quad flat pack transceiver zipwireplus dsp/transceiver block uart universal asy n chronous receive transm it uip user interface program uni user network interface up stream fro m th e htu-r to ward s th e htu-c (in c lu d e s regenerators) utopia universal test and op erations phy interface for atm w l w a t e r l e v e l 500054d mindspeed technologies? preliminary information/mindspeed proprietary and confidential e-3
appendix e : acr ony m s and a bbr eviations m 28975 data sheet e-4 mindspeed technologies? preliminary information/mindspeed proprietary and confidential 500054d www. m i n d s p e e d . c o m general information: u.s. and canada: (800) 854-8099 international: (949) 483-6996 headquarters - new port beach 4311 jamboree rd. p.o. box c new port beach, ca. 92658

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